According to one aspect of this disclosure, a
display device includes: a timing controller configured to generate image data, a
data control signal, and a
gate control signal, the
gate control signal including a cutoff
clock signal; a data driver configured to generate a plurality of data signals corresponding to the image data based on the
data control signal, and output the data signals to a plurality of
data lines; a
gate driver configured to generate a plurality of gate signals based on the
gate control signal, and output the gate signals to a plurality of gate lines; and a display panel including a plurality of pixels disposed in a display area and connected to the plurality of
data lines and the plurality of gate lines. The timing controller stops the transmission of image data during a period when a low-power drive signal is at a logic high level, and the
gate driver changes the pulse width of a gate signal among the plurality of gate signals that has a conduction level pulse overlapping with the period when the low-power drive signal is at a logic high level.