Display device

Abstract

According to one aspect of this disclosure, a display device includes: a timing controller configured to generate image data, a data control signal, and a gate control signal, the gate control signal including a cutoff clock signal; a data driver configured to generate a plurality of data signals corresponding to the image data based on the data control signal, and output the data signals to a plurality of data lines; a gate driver configured to generate a plurality of gate signals based on the gate control signal, and output the gate signals to a plurality of gate lines; and a display panel including a plurality of pixels disposed in a display area and connected to the plurality of data lines and the plurality of gate lines. The timing controller stops the transmission of image data during a period when a low-power drive signal is at a logic high level, and the gate driver changes the pulse width of a gate signal among the plurality of gate signals that has a conduction level pulse overlapping with the period when the low-power drive signal is at a logic high level.

Description

[0001] Cross-references to related applications This application claims priority to Korean Patent Application No. 10-2024-0200091, filed with the Korean Intellectual Property Office on December 30, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a display device, and more specifically, to a display device capable of low-power transmission drive. Background Technology

[0003] Display devices include liquid crystal displays (LCDs), electroluminescent displays, and quantum dot displays (QDs). Based on the material of the light-emitting layer, electroluminescent displays can be classified into inorganic light-emitting displays and organic light-emitting displays.

[0004] Low-power transfer drive (LPTD) is being developed as a way to reduce power consumption in such display devices. When the low-power transfer drive is activated, the source driver IC stores image data in memory when two or more pixel rows display an image of the same grayscale in an area covered by the source driver IC. The source driver IC can periodically read the image data stored in the online buffer and transfer the image data to the display panel. Although images of the same grayscale are displayed in pixel rows, the image data is not transferred from the timing controller to the source driver IC. Therefore, the power consumption of the timing controller can be reduced in the low-power transfer drive. Summary of the Invention

[0005] One object of this disclosure is to provide a display device that can minimize power consumption.

[0006] The purpose of this disclosure is not limited to the purposes described above, and other purposes not mentioned above may be clearly understood by those skilled in the art from the following description.

[0007] According to one aspect of this disclosure, a display device includes: a timing controller configured to generate image data, a data control signal, and a gate control signal, the gate control signal including a cutoff clock signal; a data driver configured to generate a plurality of data signals corresponding to the image data based on the data control signal and output the data signals to a plurality of data lines; a gate driver configured to generate a plurality of gate signals and output the gate signals to a plurality of gate lines; and a display panel including a plurality of pixels disposed in a display area and connected to the plurality of data lines and the plurality of gate lines, wherein the timing controller stops the transmission of image data in a region where a low-power drive signal is at a logic high level, and the gate driver can change the pulse width of a gate signal among the plurality of gate signals that has a conduction level pulse overlapping with the region where the low-power drive signal is at a logic high level.

[0008] According to one aspect of this disclosure, a display device includes: a timing controller configured to generate image data, a data control signal, and a gate control signal, the gate control signal including a cutoff clock signal; a data driver configured to generate a plurality of data signals corresponding to the image data based on the data control signal; and a gate driver configured to generate a plurality of gate signals based on an on-clock signal and a cutoff clock signal included in the gate control signal, wherein the timing controller stops the transmission of image data during a period when the low-power drive signal is at a logic high level, and the timing controller can change the pulse width of a pulse in the plurality of pulses included in the cutoff clock signal that overlaps with the period when the low-power drive signal is at a logic high level.

[0009] Further details of the exemplary embodiments are included in the detailed description and the accompanying drawings.

[0010] According to this disclosure, when multiple pixel rows display an image with the same grayscale, the transmission of image data corresponding to at least a portion of the pixel rows displaying the same grayscale image can be stopped. Therefore, the power consumption for data transmission can be reduced.

[0011] Furthermore, during periods when image data transmission is paused, this disclosure allows the cutoff clock signal used to generate the gate signal to be shifted in a specific direction. Therefore, the falling edge of the gate signal is shifted in response to the cutoff clock signal to reduce the pulse width of the gate signal, thereby further reducing the power consumption of the gate driver.

[0012] Furthermore, during periods when image data transmission is paused, this disclosure allows for an increase in the pulse width of the cutoff clock signal used to generate the gate signal. Therefore, the gate pulse modulation (GPM) portion increases at the falling edge of the gate signal in response to the pulse width of the cutoff clock signal, thereby further reducing the power consumption of the gate driver.

[0013] The effects of this disclosure are not limited to those illustrated above, and may include a wide variety of other effects. Attached Figure Description

[0014] The above and other aspects, features and advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram of a display device according to exemplary embodiments of the present disclosure.

[0015] Figure 2 It is shown that it includes Figure 1 A block diagram of an example timing controller, data driver, and display panel in a display device.

[0016] Figure 3 It is shown that it includes Figure 1 A block diagram of an example timing controller and data driver in a display device.

[0017] Figure 4 It is used to describe Figure 1 A diagram illustrating an example of a low-power transmission drive for a display device.

[0018] Figure 5 It is shown that it includes Figure 1 A block diagram of an example timing controller and gate driver in a display device.

[0019] Figures 6A to 6C It is shown Figure 5 A waveform diagram illustrating the operation of an example gate driver.

[0020] Figure 7A and Figure 7B It is shown Figure 5 Waveform diagram of an example of low-power full-speed drive operation of the timing controller and gate driver.

[0021] Figure 8A and Figure 8B It is shown Figure 5 Waveform diagram of another example of low-power full-speed drive operation of the timing controller and gate driver. Detailed Implementation

[0022] The advantages and features of this disclosure, as well as methods for achieving such advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0023] The shapes, dimensions, ratios, angles, quantities, etc. illustrated in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “including” as used herein are generally intended to allow for the addition of additional components, unless the term is used in conjunction with the term “only.” Any reference to the singular may include the plural unless explicitly stated otherwise.

[0024] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0025] When using terms such as “above,” “over,” “below,” and “adjacent” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless the term is used with the terms “immediately adjacent” or “directly.”

[0026] When one element or layer is placed "on" another element or layer, another layer or element can be directly inserted onto or between that other element.

[0027] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component referred to below may be the second component in the technical concept of this disclosure.

[0028] The same reference numerals generally denote the same elements throughout the disclosure.

[0029] The dimensions and thicknesses of each component illustrated in the accompanying drawings are for ease of description and this disclosure is not limited to the dimensions and thicknesses of the illustrated components.

[0030] The features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be associated and operated in a variety of technical ways, and the embodiments may be implemented independently of each other or in relation to each other.

[0031] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 This is a block diagram of a display device according to exemplary embodiments of the present disclosure.

[0033] Reference Figure 1 The display device 100 according to an exemplary embodiment of the present disclosure may include a timing controller 110, a gate driver 120, a data driver 130, and a display panel 140.

[0034] Display panel 140 can generate an image to be provided to a user. For example, display panel 140 may include a plurality of pixels PX, each of which is provided with pixel circuitry. Each of the plurality of pixels PX is connected to a corresponding gate line GL and a corresponding data line DL to display an image in response to a gate signal provided to the gate line GL and a data signal provided to the data line DL.

[0035] The timing controller 110 can control the gate driver 120 and the data driver 130 based on an input image RGB and a control signal CS provided from an external source (e.g., a host system). For example, the input control signal CS includes timing signals such as a horizontal sync signal, a vertical sync signal, a data enable signal, and a clock signal, and the timing controller 110 can generate a gate control signal GCS and a data control signal DCS based on the control signal CS. The gate control signal GCS can be provided to the gate driver 120, and the data control signal DCS can be provided to the data driver 130.

[0036] In addition, the timing controller 110 rearranges the input image RGB in a digital video data format to match the resolution of the display panel 140, thereby generating image data DATA and providing the image data to the data driver 130.

[0037] According to embodiments, timing controller 110 can send signals to and receive signals from other components through one or more predetermined interfaces. For example, the interface may include an embedded point-to-point clock interface (EPI). In this case, timing controller 110 can configure data control signals DCS and image data DATA in EPI transmission format, and then provide the data control signals DCS and image data DATA to data driver 130. However, embodiments of this disclosure are not limited thereto, and the interface may include a Serial Personal Interface (SPI) and a Low Voltage Differential Signaling (LVDS) interface.

[0038] The gate driver 120 can generate a gate signal based on the gate control signal GCS and output the gate signal to multiple gate lines GL. For example, the gate driver 120 can sequentially output the gate signal to multiple gate lines GL on a pixel-row basis.

[0039] In one embodiment, the gate driver 120 may include a level shifter. For example, the gate control signal GCS includes an on-clock signal, an off-clock signal, a start signal, etc., and the level shifter may generate multiple gate clock signals and multiple gate start signals based on the on-clock signal, the off-clock signal, the start signal, etc. The gate driver 120 may generate multiple gate signals based on the multiple gate clock signals and multiple gate start signals generated by the level shifter.

[0040] The data driver 130 converts digital image data DATA provided by the timing controller 110 into analog data signals based on the data control signal DCS, so as to supply the analog data signals to multiple data lines DL.

[0041] For example, the data driver 130 can generate a sampling signal based on the data control signal DCS, latch the image data DATA based on the sampling signal to convert the image data DATA into an analog data signal (data voltage), and then supply the data signal to multiple data lines DL. For example, the data control signal DCS may include a data clock signal, line latching signals, etc., for generating the data signal.

[0042] In one embodiment, the data driver 130 may include at least one source driver integrated circuit. Here, each of the at least one source driver integrated circuit included in the data driver 130 may separate the data control signal DCS and the image data DATA in an EPI transmission format transmitted from the timing controller 110.

[0043] In addition, each of the at least one source driver integrated circuits included in the data driver 130 generates a data signal based on the data control signal DCS and the image data DATA, and supplies the data signal to multiple data lines DL through multiple channels.

[0044] In an embodiment, the display device 100 can operate in a low-power transmission drive (LPTD) mode. For example, the timing controller 110 can detect whether two or more pixel rows among a plurality of pixel rows included in the display panel 140 display the same grayscale based on an input image RGB input from an external source (e.g., a host system). When two or more pixel rows display the same grayscale, the low-power transmit driver of the timing controller 110 transmits image data DATA to the data driver 130 in response to the first pixel row among the two or more pixel rows displaying the same grayscale, and then stops transmitting image data DATA to the data driver 130 for a period corresponding to the remaining pixel rows. Therefore, power consumption due to data transmission of the timing controller 110 can be reduced.

[0045] For a more detailed description of this low-power transmission drive method, please refer to [link / reference]. Figures 2 to 4 .

[0046] Figure 2 It is shown that it includes Figure 1 A block diagram of an example timing controller, data driver, and display panel in a display device.

[0047] Figure 3 It is shown that it includes Figure 1 A block diagram of an example timing controller and data driver in a display device.

[0048] Figure 4 It is used to describe Figure 1 A diagram illustrating an example of a low-power transmission drive for a display device.

[0049] at the same time, Figure 2 An exemplary illustration shows a data driver 130 including four source driver integrated circuits DIC1 to DIC4. However, this is provided merely for illustrative purposes, and the number of source driver integrated circuits DIC1 to DIC4 included in the data driver 130 can be determined depending on the size and resolution of the display panel 140. Hereinafter, for ease of description, the data driver 130 will be described as including four source driver integrated circuits DIC1 to DIC4.

[0050] Reference Figure 1 and Figure 2 The timing controller 110 can be connected to multiple source driver integrated circuits DIC1 to DIC4 included in the data driver 130 via at least one interface EPI.

[0051] For example, refer to together Figure 3 Each of the multiple transmitters Tx1 to Tx4 included in the transmitter 112 of the timing controller 110 can be connected to multiple source driver integrated circuits DIC1 to DIC4 included in the data driver 130 via multiple interfaces EPI1 to EPI4 (e.g., EPI line pairs, 1:1 form, i.e. point-to-point).

[0052] More specifically, image data DATA and data control signals DCS generated based on the input image RGB of timing controller 110 are converted into serial data and provided to a plurality of source driver integrated circuits DIC1 to DIC4 included in data driver 130 via interface EPI connected to transmitter 112. For this purpose, transmitter 112 included in timing controller 110 may include a plurality of transmitters Tx1 to Tx4 corresponding to the number of source driver integrated circuits DIC1 to DIC4. That is, each of the plurality of transmitters Tx1 to Tx4 in transmitter 112 included in timing controller 110 is connected to the corresponding source driver integrated circuits DIC1 to DIC4 via multiple interfaces EPI1 to EPI4 to transmit the serial data type image data DATA and data control signals DCS to the source driver integrated circuits DIC1 to DIC4.

[0053] Each of the multiple source driver integrated circuits DIC1 to DIC4 included in the data driver 130 may include a register, a latch, a digital-to-analog converter, an output buffer, etc.

[0054] Each of the source driver integrated circuits DIC1 to DIC4 can receive data control signals DCS and image data DATA from the timing controller 110 through the corresponding interfaces EPI1 to EPI4, and generate data signals based on the data control signals.

[0055] For example, each of the source driver integrated circuits DIC1 to DIC4 recovers its clock from the signal provided by the timing controller 110 through the corresponding interface EPI1 to EPI4 and fixes the phase and frequency of the internal clock to output a lock signal. The timing controller 110 can provide a data packet containing image data DATA and data control signal DCS to the corresponding source driver integrated circuits DIC1 to DIC4 through the corresponding interface EPI1 to EPI4 when it receives the lock signal from the last source driver integrated circuit.

[0056] The display area AA of the display panel 140 may include multiple display areas A1 to A4, each corresponding to a source driver integrated circuit DIC1 to DIC4. For example, each display area is connected to one of the source driver integrated circuits DIC1 to DIC4 to receive data signals. Pixel PX disposed in each of the display areas A1 to A4 can display an image based on the data signals output from the corresponding source driver integrated circuits DIC1 to DIC4.

[0057] In the embodiment, as described above, when the display device 100 is operating in a low-power transmission drive mode, the timing controller 110 may stop data transmission to at least one of the plurality of source driver integrated circuits DIC1 to DIC4 included in the data driver 130.

[0058] For example, refer to Figure 3 The timing controller 110 may include a low-power transmit driver 111 and a transmitter 112. The low-power transmit driver 111 may provide a low-power drive signal LPTD to the transmitter 112. Here, based on the signal level of the low-power drive signal LPTD, it can be determined whether to stop data transmission from the transmitter 112 to the data driver 130 through the interface EPI.

[0059] For example, the low-power transmit driver 111 can provide a first low-power drive signal LPTD1 to the first transmitter Tx1, a second low-power drive signal LPTD2 to the second transmitter Tx2, a third low-power drive signal LPTD3 to the third transmitter Tx3, and a fourth low-power drive signal LPTD4 to the fourth transmitter Tx4. Here, each of the plurality of transmitters Tx1 to Tx4 of transmitter 112 can determine whether to stop data transmission through interface EPI based on the signal level of the corresponding low-power drive signal LPTD. For example, when the signal level of the corresponding low-power drive signal LPTD is logic high, each of the plurality of transmitters Tx1 to Tx4 can stop data transmission to the corresponding interfaces EPI1 to EPI4, and when the signal level of the low-power drive signal LPTD is logic low, image data DATA and data control signal DCS are transmitted to the corresponding source driver integrated circuits DIC1 to DIC4 through the corresponding interfaces EPI1 to EPI4.

[0060] For a more detailed description of the low-power transmission drive method, please refer to [link / reference]. Figure 4 When multiple pixels PX in the display area AA of the display panel 140 are set in multiple pixel rows PXL(1) to PXL(n) (where n is an integer greater than 0), when two or more pixel rows of multiple pixel rows PXL(1) to PXL(n) display images with the same grayscale, the timing controller 110 can transmit the image data DATA corresponding to the first pixel row of the two or more pixel rows that display images with the same grayscale to the data driver 130, and then stop transmitting the image data DATA to the remaining pixel rows.

[0061] For example, such as Figure 4 As shown, when the first pixel row PXL(1) to the (i-1)th pixel row PXL(i-1) (where i is an integer greater than 0 and less than n) of the third display area A3 of the display area AA displays images of different gray levels, the third-2nd display area A32 (corresponding to the i-th pixel row PXL(i) to the (j-1)th pixel row PXL(j-1) (j is an integer greater than i and less than n) of the third display area A3 displays images of the same gray level, and the third-3rd display area A33 (corresponding to the (j)th pixel row PXL(j) to the (n)th pixel row PXL(n) of the third display area A3 displays images of different gray levels, the timing controller 110 can transmit the image data DATA corresponding to the third-1st display area A31 and the third-3rd display area A33 to the third source driver integrated circuit DIC3 (which provides data signals to the third display area A3) during the corresponding time period. Figure 4It is shown as "EPI Tx On"), and can stop at least a portion of the transmission of image data DATA corresponding to the 3-2 display area A32 (in Figure 4 It is shown as "EPI Tx Off" in the image.

[0062] For example, the third transmitter Tx3 included in the transmitter 112 of the timing controller 110 can send the image data DATA of the i-th pixel row PXL(i) to the third source driver integrated circuit DIC3 via the third interface EPI3 during the i-th horizontal time period in a frame.

[0063] Furthermore, during the horizontal period when the image data DATA of the remaining pixel rows displaying the same grayscale in the 3-2 display area A32 should be transmitted (e.g., pixel row (i+1) PXL(i+1) to pixel row (j-1) PXL(j-1)), the third transmitter Tx3 can be driven at low power by stopping the transmission of image data DATA via the third interface EPI3.

[0064] For example, the third low-power drive signal LPTD3 can have a logic high level in the interval corresponding to the horizontal time period of the pixel row with the same gray level of the image data DATA to be transmitted to the 3-2 display area A32, and a logic low level in other intervals.

[0065] Here, when the transmission of image data DATA stops, the third source driver integrated circuit DIC3 can store the data signal generated based on the image data DATA of the i-th pixel row PXL(i) provided by the timing controller 110 in the embedded memory (or channel input buffer / line buffer), and repeatedly output the data stored in the remaining pixel rows of the 3-2 display area A32 that display the same gray level (e.g., the (i+1)-th pixel row PXL(i+1) to the (j-1)-th pixel row PXL(j-1)).

[0066] Subsequently, in response to the horizontal time period of the image data DATA corresponding to the last pixel row (e.g., the (j-1)th pixel row PXL(j-1)) of the same grayscale in the 3-2 display area A32, the timing controller 110 can wake up the third source driver integrated circuit DIC3, which is the corresponding source driver integrated circuit, by outputting a clock training mode via the third interface EPI3. Therefore, the third source driver integrated circuit DIC3 can normally receive the image data DATA corresponding to the j-th pixel row PXL(j) to the n-th pixel row PXL(n) from the third transmitter Tx3 of the timing controller 110 via the third interface EPI3.

[0067] As another example, such as Figure 4As shown, when display area A11 of display area AA displays images of different grayscale, display area A12 of display area AA displays images of the same grayscale, and display area A13 of display area AA displays images of different grayscale, the timing controller 110 can transmit the image data DATA corresponding to display area A11 and display area A13 of display area AA to the first source driver integrated circuit DIC1 that provides data signals to display area A1 during the corresponding time period. Figure 4 The text is incomplete and contains several grammatical errors and inconsistencies. A proper translation is not possible without the full context and complete sentences. Figure 4 It is shown as "EPI Tx Off" in the image.

[0068] For example, the first transmitter Tx1 included in the transmitter 112 of the timing controller 110 can transmit the image data DATA of the k-th pixel row PXL(k) to the first source driver integrated circuit DIC1 through the first interface EPI1 during the k-th horizontal time period within a frame.

[0069] Furthermore, during the horizontal period when the image data DATA of the remaining pixel rows displaying the same gray level in the first-second display area A12 is to be transmitted (e.g., the (k+1) pixel row PXL(k+1) to the (l-1) pixel row PXL(l-1)), the first transmitter Tx1 can be driven at low power by stopping the transmission of image data DATA via the first interface EPI1.

[0070] For example, the first low-power drive signal LPTD1 may have a logic high level in the interval corresponding to the horizontal time period of the pixel row with the same gray level of the image data DATA to be transmitted to the 1-2 display area A12, and a logic low level in other intervals.

[0071] Here, when the transmission of image data DATA stops, the first source driver integrated circuit DIC1 can store the data signal generated based on the image data DATA of the k-th pixel row PXL(k) provided by the timing controller 110 in the built-in memory (or channel input buffer), and repeatedly output the data signal stored in the remaining pixel rows of the first-second display area A12 that display the same gray level (e.g., the (k+1)-th pixel row PXL(k+1) to the (l-1)-th pixel row PXL(l-1)).

[0072] Subsequently, in response to the horizontal time period of the image data DATA corresponding to the last pixel row (e.g., the (l-1)th pixel row PXL(l-1)) of the first-second display area A12 with the same grayscale, the timing controller 110 can wake up the first source driver integrated circuit DIC1, which is the corresponding source driver integrated circuit, by outputting a clock training mode via the first interface EPI1. Therefore, the first source driver integrated circuit DIC1 can normally receive the image data DATA corresponding to the first pixel row PXL(l) to the nth pixel row PXL(n) from the first transmitter Tx1 of the timing controller 110 via the first interface EPI1.

[0073] At this time, in the case of the second display area A2 and the fourth display area A4 in the display area AA, images of different gray levels are displayed in all pixel rows (e.g., the first pixel row PXL(1) to the nth pixel row PXL(n)). Therefore, the timing controller 110 can normally transmit the image data DATA corresponding to all pixel rows to the second source driver integrated circuit DIC2 and the fourth source driver integrated circuit DIC4 that provide data signals to the second display area A2.

[0074] Figure 5 It is shown that it includes Figure 1 A block diagram of an example timing controller and gate driver in a display device.

[0075] Figures 6A to 6C It is shown Figure 5 A waveform diagram illustrating the operation of an example gate driver.

[0076] at this time, Figures 6A to 6C The diagram shows multiple clock signals CLK generated by the level shifter 121, including the first clock signal CLK1 to the fourth clock signal CLK4. However, this is illustrative and the number of clock signals CLK generated by the level shifter 121 can be modified in various ways.

[0077] Reference Figure 1 and Figure 5 The gate driver 120 generates multiple gate signals Gate1 to Gate4 based on the gate control signal GCS provided from the timing controller 110, and sequentially provides the gate signals to multiple gate lines GL.

[0078] Therefore, in this embodiment, the gate driver 120 may include a level shifter 121 and a gate signal generator 122.

[0079] The level shifter 121 can generate multiple gate clock signals CLK and gate start signals GVST based on the start signal VST, turn-on clock signal ON_CLK and turn-off clock signal OFF_CLK included in the gate control signal GCS provided from the timing controller 110, and provide them to the gate signal generator 122.

[0080] Gate signal generator 122 can generate multiple gate signals Gate1 to Gate4 based on multiple gate clock signals CLK and gate start signal GVST provided from level shifter 121. For example, gate signal generator 122 may include a shift register.

[0081] More specifically, refer to Figure 6A Each of the ON clock signal (ON_CLK) and the OFF clock signal (OFF_CLK) may include multiple pulses formed at a preset period. For example, each of the ON clock signal (ON_CLK) and the OFF clock signal (OFF_CLK) may be a signal that periodically has an ON level and an OFF level. For example, the ON clock signal (ON_CLK) and the OFF clock signal (OFF_CLK) may have the same period.

[0082] The level shifter 121 generates multiple gate clock signals CLK1 to CLK4 based on the on clock signal ON_CLK and the off clock signal OFF_CLK, and shifts the voltage level of each of the multiple gate clock signals CLK1 to CLK4 to a voltage level in which the transistor can operate, so as to provide the voltage level to the gate signal generator 122.

[0083] For example, level shifter 121 can generate multiple gate clock signals CLK1 to CLK4 with rising and falling edges, the rising and falling edges corresponding to the rising or falling edge of each of the turn-on clock signal ON_CLK and the turn-off clock signal OFF_CLK.

[0084] For example, such as Figure 6A As shown, the level shifter 121 can generate a rising edge of a pulse included in the first gate clock signal CLK1 in response to a first rising edge included in the turn-on clock signal ON_CLK during a frame period, and generate a falling edge of the pulse included in the first gate clock signal CLK1 in response to a second rising edge included in the turn-off clock signal OFF_CLK.

[0085] Therefore, the pulse included in the first gate clock signal CLK1 can have a conduction-level pulse comprising rising and falling edges corresponding to the first rising edge included in the turn-on clock signal ON_CLK and the second rising edge included in the cut-off clock signal OFF_CLK, respectively. Furthermore, the first gate clock signal CLK1 is configured to similarly provide four pulses of the turn-on clock signal ON_CLK and the cut-off clock signal OFF_CLK to have conduction-level pulses.

[0086] Furthermore, level shifter 121 can generate second gate clock signals CLK2 to fourth gate clock signals CLK4 in a manner similar to the first gate clock signal CLK1. For example, the first gate clock signals CLK1 to fourth gate clock signals CLK4 can have the same pulse width and the same period, and can have waveforms whose phases do not overlap. For example, the second gate clock signal CLK2 can be configured as a signal shifted by the periods of the on-clock signal ON_CLK and the off-clock signal OFF_CLK in the first gate clock signal CLK1, the third gate clock signal CLK3 can be configured as a signal shifted by the periods of the on-clock signal ON_CLK and the off-clock signal OFF_CLK in the second gate clock signal CLK2, and the fourth gate clock signal CLK4 can be configured as a signal shifted by the periods of the on-clock signal ON_CLK and the off-clock signal OFF_CLK in the third gate clock signal CLK3.

[0087] Gate driver 120 can generate multiple gate signals Gate1 to Gate4 based on multiple gate clock signals CLK1 to CLK4 provided from level shifter 121. For example, gate driver 120 can generate multiple gate signals Gate1 to Gate4 having a turn-on level pulse corresponding to any one of the turn-on level pulses of each of the multiple gate clock signals CLK1 to CLK4.

[0088] However, embodiments of this disclosure are not limited thereto, and the level shifter 121 can be controlled to include a gate pulse modulation (hereinafter referred to as "GPM") period at the falling edge of each of the plurality of pulses included in each of the plurality of clock signals CLK1 to CLK4. In this case, recoil occurring in the pixel PX to which the gate signal is provided can be compensated. For this purpose, refer to Figure 5 The level shifter 121 may also include a recoil compensator 1211.

[0089] Specifically, such as Figure 6BAs shown, the level shifter 121 can generate a rising edge of a pulse included in the first gate clock signal CLK1 in response to a first rising edge included in the turn-on clock signal ON_CLK during a frame period, and generate a falling edge of the pulse included in the first gate clock signal CLK1 in response to a second falling edge included in the turn-off clock signal OFF_CLK.

[0090] Therefore, the pulse included in the first gate clock signal CLK1 can have a conduction level pulse that includes rising and falling edges corresponding to the first rising edge included in the conduction clock signal ON_CLK and the second falling edge included in the cutoff clock signal OFF_CLK, respectively.

[0091] Here, the recoil compensator 1211 can be controlled to include a GPM period at the falling edge of a pulse included in the first gate clock signal CLK1 during the period from the time point from the generation of the second rising edge included in the cutoff clock signal OFF_CLK to the time point from the generation of the second falling edge. For example, as Figure 6B As shown, the recoil compensator 1211 can control a pulse included in the first gate clock signal CLK1 to gradually decrease from the on level to the off level.

[0092] However, the embodiments disclosed herein are not limited thereto, and as follows Figure 6C As shown, the recoil compensator 1211 can perform control to gradually reduce a pulse included in the first gate clock signal CLK1 from the on level to the off level.

[0093] Furthermore, as described above, the first gate clock signal CLK1 is configured to provide four pulses of the turn-on clock signal ON_CLK and the turn-off clock signal OFF_CLK in a similar manner to have a turn-on level. Additionally, as described above, the level shifter 121 can generate second gate clock signals CLK2 to fourth gate clock signals CLK4, including GPM periods, for each pulse in a manner similar to the first gate clock signal CLK1.

[0094] Figure 7A and Figure 7B It is shown Figure 5 Waveform diagram of an example of low-power full-speed drive operation of the timing controller and gate driver.

[0095] Reference Figures 1 to 3 , Figure 5 and Figure 7A As described above, the timing controller 110 can determine whether to stop transmitting image data DATA to the data driver 130 based on the signal level of the low-power drive signal LPTD.

[0096] For example, such as Figure 7A As shown, when the low-power drive signal LPTD is in the logic low level range, the timing controller 110 transmits the image data DATA normally to the data driver 130, and the data driver 130 can output the data signal Vdata corresponding to the image data DATA provided by the timing controller 110.

[0097] Conversely, when the low-power drive signal LPTD is at a logic high level, the timing controller 110 stops transmitting image data DATA to the data driver 130, and the data driver 130 can output the data signal stored in the embedded memory in a corresponding manner when the low-power drive signal LPTD is at a logic high level.

[0098] For example, such as Figure 7A As shown, the data driver 130 can output a data signal Vdata corresponding to the third level period in response to the fourth level period, and output a data signal Vdata corresponding to the ninth level period in response to the tenth to twelfth level periods in response to the period when the low power drive signal LPTD has a logic high level.

[0099] In an embodiment, in a low-power transmission drive mode, the timing controller 110 may shift at least a portion of the pulses included in the cutoff clock signal OFF_CLK provided to the gate driver 120. For example, the timing controller 110 may change the pulse period of at least a portion of the pulses included in the cutoff clock signal OFF_CLK.

[0100] For example, refer to together Figure 7B The timing controller 110 can control at least one pulse in the negative direction (e.g., the cutoff clock signal OFF_CLK included in a plurality of pulses with a constant period PD and overlapping with the interval of the low-power drive signal LPTD having a logic high level) in the interval of the low-power drive signal LPTD. Figure 7B (As shown) Up shift.

[0101] For example, timing controller 110 can shift the timing of each of the rising and falling edges of at least one pulse in the plurality of pulses included in the cutoff clock signal OFF_CLK that overlaps with the interval of the low power drive signal LPTD having a logic high level in the negative direction.

[0102] According to an embodiment, the timing controller 110 may shift the pulse width of each of the rising and falling edges of at least one pulse in the negative direction of the plurality of pulses included in the cutoff clock signal OFF_CLK, but is not limited thereto. For example, the timing controller 110 may shift the pulse width of each of the plurality of pulses included in the cutoff clock signal OFF_CLK by a multiple of the rising and falling edges of at least one pulse in the negative direction.

[0103] For example, as referenced Figure 6A As stated, when the falling edge of the pulse included in the gate clock signal CLK corresponds to the rising edge included in the cutoff clock signal OFF_CLK, such as Figure 7A and Figure 7B As shown, the falling edge of the turn-on level pulse of each of the third gate signal Gate3, the fourth gate signal Gate4, the ninth gate signal Gate9, the tenth gate signal Gate10, the eleventh gate signal Gate11, and the twelfth gate signal Gate12 can be shifted in the negative direction in response to a pulse that is shifted in the negative direction among the multiple pulses included in the cutoff clock signal OFF_CLK.

[0104] Simultaneously, the multiple pulses included in the ON_CLK turn-on clock signal provided from the timing controller 110 to the gate driver 120 can have a constant period PD without shifting in a specific direction. Therefore, the rising edge of the turn-on level pulse included in each of the multiple gate signals does not shift in a specific direction to correspond to the ON_CLK turn-on clock signal and has a constant period; however, the falling edge of the turn-on level pulse of the gate signal included in the OFF_CLK turn-off clock signal, which has a falling edge corresponding to a pulse shifted in the negative direction, can be shifted in the negative direction. Therefore, the pulse width of the gate signal overlapping with the interval where the low-power drive signal LPTD is at a logic high level (i.e., the gate signal supplied to the pixel row corresponding to the horizontal period when image data DATA is not transmitted from the timing controller 110 to the data driver 130) can be reduced.

[0105] As described above, even if the pulse width of the gate signal supplied to the pixel row corresponding to the horizontal period when the image data DATA is not transmitted from the timing controller 110 to the data driver 130 is reduced, the same data signal Vdata will still be supplied to the pixel row, so that the data signal Vdata can be written to the pixel PX normally, and the charging time decreases as the pulse width of the gate signal decreases, thereby further reducing the power consumption of the gate driver 120.

[0106] Figure 8A and Figure 8B It is shown Figure 5Waveform diagram of another example of low-power full-speed drive operation of the timing controller and gate driver.

[0107] at the same time, Figure 8A and Figure 8B It shows Figure 7A and Figure 7B Therefore, the modified embodiment will not be described redundantly again.

[0108] Reference Figures 1 to 3 , Figure 5 and Figure 8A In low-power transmission drive mode, timing controller 110 can change the pulse width of at least a portion of the pulses included in the cutoff clock signal OFF_CLK supplied to gate driver 120. For example, timing controller 110 can increase the pulse width of at least a portion of the pulses included in the cutoff clock signal OFF_CLK.

[0109] For example, refer to together Figure 8B The timing controller 110 can change the pulse width of at least one pulse from among the multiple pulses included in the cutoff clock signal OFF_CLK, each having a first pulse width PS1, that overlaps with an interval having a logic high level with the low-power drive signal LPTD, to a second pulse width PS2. For example, the second pulse width PS2 can be greater than the first pulse width PS1. For example, the second pulse width PS2 can be twice the first pulse width PS1, but is not limited thereto, and the second pulse width PS2 can be set differently.

[0110] For example, the timing controller 110 can shift the rising edge time of at least one pulse in the plurality of pulses included in the cutoff clock signal OFF_CLK that overlaps with the interval where the low-power drive signal LPTD has a logic high level in the negative direction. Here, the falling edge time of the at least one pulse may not be shifted in a specific direction. That is, the falling edge of the at least one pulse may be fixed. Therefore, the pulse width of the at least one pulse in the plurality of pulses included in the cutoff clock signal OFF_CLK that overlaps with the interval where the low-power drive signal LPTD has a logic high level can be increased.

[0111] According to an embodiment, the timing controller 110 may shift the rising edge of at least one pulse in the negative direction by altering the pulse width of each of the plurality of pulses included in the cutoff clock signal OFF_CLK, but is not limited thereto. For example, the timing controller 110 may shift the rising edge of at least one pulse in the negative direction by altering the pulse width of each of the plurality of pulses included in the cutoff clock signal OFF_CLK by a multiple of the pulse width.

[0112] In this case, the falling edge of at least one of the multiple pulses included in the cutoff clock signal OFF_CLK is not shifted in a specific direction, but is fixed, and only the rising edge is shifted in the negative direction, so the pulse width of at least one pulse can be increased. For example, the pulse width of at least one pulse can be increased by the degree of rising edge shift.

[0113] For example, as referenced Figure 6B As stated, when the falling edge of the pulse included in the gate clock signal CLK corresponds to the falling edge included in the cutoff clock signal OFF_CLK, such as Figure 8A and Figure 8B As shown, in response to the pulses with variable pulse widths among the multiple pulses included in the cutoff clock signal OFF_CLK, the falling range of the pulses at the conduction level of each of the third gate signal Gate3, the fourth gate signal Gate4, the ninth gate signal Gate9, the tenth gate signal Gate10, the eleventh gate signal Gate11, and the twelfth gate signal Gate12 can be increased.

[0114] Therefore, the GPM period can be increased for the gate signal that overlaps with the interval where the low-power drive signal LPTD is at a logic high level (i.e., the gate signal supplied to the pixel row corresponding to the horizontal period when the image data DATA is not transmitted from the timing controller 110 to the data driver 130).

[0115] As described above, even if the GPM range of the gate signal supplied to the pixel row corresponding to the horizontal period when the image data DATA is not transmitted from the timing controller 110 to the data driver 130 increases, the same data signal Vdata will be supplied to the pixel row, so that the data signal Vdata can be written to the pixel PX normally, and the charging time decreases as the GPM range of the gate signal increases, so that the power consumption of the gate driver 120 can be further reduced.

[0116] At the same time, even Figure 8A and Figure 8B The diagram illustrates that the pulse of the turn-on level included in the gate signal gradually decreases during the GPM period, but exemplary embodiments of this disclosure are not limited thereto. (See reference...) Figure 6C The pulses of the conduction level included in the gate signal can be gradually reduced during the GPM period.

[0117] As described above, in the display device 100 according to an exemplary embodiment of the present disclosure, when multiple pixel rows display an image of the same grayscale, the transmission of image data corresponding to at least a portion of the pixel rows displaying the image of the same grayscale can be stopped. Therefore, the power consumption of data transmission can be reduced.

[0118] Furthermore, during the period when image data transmission is stopped, the display device 100 according to an exemplary embodiment of the present disclosure can shift the cutoff clock signal, which is used to generate the gate signal, in a specific direction. Therefore, the falling edge of the gate signal shifts in response to the cutoff clock signal to reduce the pulse width of the gate signal, thereby further reducing the power consumption of the gate driver 120.

[0119] Furthermore, during the period when image data transmission is stopped, the display device 100 according to an exemplary embodiment of the present disclosure may increase the pulse width of the cutoff clock signal, which is used to generate the gate signal, in the turn-on clock signal and the cutoff clock signal. Therefore, in response to the pulse width of the cutoff clock signal, a gate pulse modulation (GPM) interval is added at the falling edge of the gate signal, thereby further reducing the power consumption of the gate driver 120.

[0120] Exemplary embodiments of this disclosure can also be described as follows: According to one aspect of this disclosure, a display device includes: a timing controller configured to generate image data, a data control signal, and a gate control signal, the gate control signal including a cutoff clock signal; a data driver configured to generate a plurality of data signals corresponding to the image data based on the data control signal and output the data signals to a plurality of data lines; a gate driver configured to generate a plurality of gate signals and output the gate signals to a plurality of gate lines; and a display panel including a plurality of pixels disposed in a display area and connected to the plurality of data lines and the plurality of gate lines, wherein the timing controller stops the transmission of image data in a region where a low-power drive signal is at a logic high level, and the gate driver can change the pulse width of a gate signal among the plurality of gate signals having a conduction level pulse that overlaps with the region where the low-power drive signal is at a logic high level.

[0121] According to another feature of this disclosure, the gate driver may include: a level shifter configured to generate a plurality of gate clock signals based on an on-clock signal and an off-clock signal included in a gate control signal; and a gate signal generator configured to generate a plurality of gate signals based on the plurality of gate clock signals.

[0122] According to another feature of this disclosure, the gate driver can reduce the pulse width of a gate signal among a plurality of gate signals that has a conduction level pulse overlapping with a section where the low-power drive signal is logic high.

[0123] According to another feature of this disclosure, the timing controller can shift the pulses in the negative direction that overlap with the intervals where the low-power drive signal is at a logic high level among the multiple pulses included in the cutoff clock signal.

[0124] According to another feature of this disclosure, the falling edge of a gate signal among a plurality of gate signals, having a falling edge corresponding to a pulse included in the cutoff clock signal and shifted in the negative direction, may be shifted in the negative direction.

[0125] According to another feature of this disclosure, the rising edge of each of the plurality of gate signals can be fixed.

[0126] According to another feature of this disclosure, the timing controller can shift the pulse width of each pulse in the multiple pulses included in the cutoff clock signal that overlaps with the interval where the low-power drive signal is at a logic high level.

[0127] Each of the plurality of gate signals includes a gate pulse modulation period in which the signal level decreases stepwise or gradually at the falling edge, and the gate driver can change the length of the gate pulse modulation period of the gate signal having a turn-on level pulse that overlaps with the interval where the low-power drive signal is logic high.

[0128] According to another feature of this disclosure, the timing controller can increase the pulse width of the pulses in the multiple pulses included in the cutoff clock signal that overlap with the interval where the low-power drive signal is at a logic high level.

[0129] According to another feature of this disclosure, the timing controller can shift the rising edge of a pulse in the negative direction of a plurality of pulses included in the cutoff clock signal that overlaps with the interval where the low-power drive signal is at a logic high level.

[0130] According to another feature of this disclosure, the gate pulse modulation period of the gate signal among the plurality of gate signals, which has a falling edge corresponding to a pulse included in the cutoff clock signal and having an increased pulse width, can be increased.

[0131] According to another feature of this disclosure, the timing controller can double the pulse width of the pulses in the multiple pulses included in the cutoff clock signal that overlap with the interval where the low-power drive signal is at a logic high level.

[0132] According to another feature of this disclosure, the timing controller can shift the pulse width of each of the multiple pulses included in the cutoff clock signal by the rising edge of the pulse that overlaps with the interval where the low-power drive signal is at a logic high level.

[0133] According to another feature of this disclosure, the low-power drive signal may have a high logic level corresponding to a horizontal time period of at least two pixel rows of an image displaying the same grayscale in a plurality of pixel rows of a display area.

[0134] According to another feature of this disclosure, the level shifter may include a recoil compensator that reduces or gradually decreases the signal level at the falling edge.

[0135] According to another feature of this disclosure, the position of the falling edge of each of the plurality of gate signals can be fixed.

[0136] According to one aspect of this disclosure, a display device includes: a timing controller configured to generate image data, a data control signal, and a gate control signal, the gate control signal including a cutoff clock signal; a data driver configured to generate a plurality of data signals corresponding to the image data based on the data control signal; and a gate driver configured to generate a plurality of gate signals based on an on-clock signal and a cutoff clock signal included in the gate control signal, wherein the timing controller stops the transmission of image data during a period when the low-power drive signal is at a logic high level, and the timing controller can change the pulse width of a pulse in the plurality of pulses included in the cutoff clock signal that overlaps with the period when the low-power drive signal is at a logic high level.

[0137] According to another feature of this disclosure, the gate driver can reduce the pulse width of a gate signal among a plurality of gate signals that has a conduction level pulse overlapping with a section where the low-power drive signal is logic high.

[0138] According to another feature of this disclosure, the timing controller can shift the pulses in the negative direction that overlap with the intervals where the low-power drive signal is at a logic high level among the multiple pulses included in the cutoff clock signal.

[0139] According to another feature of this disclosure, the timing controller can increase the pulse width of the pulses in the multiple pulses included in the cutoff clock signal that overlap with the interval where the low-power drive signal is at a logic high level.

[0140] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A timing controller is configured to generate image data, data control signals, and gate control signals, the gate control signals including a cutoff clock signal; A data driver is configured to generate multiple data signals corresponding to the image data based on the data control signal and output the multiple data signals to multiple data lines; A gate driver is configured to generate a plurality of gate signals based on the gate control signal and output the plurality of gate signals to a plurality of gate lines; as well as The display panel includes a plurality of pixels disposed in the display area and connected to the plurality of data lines and the plurality of gate lines. Specifically, the timing controller stops the transmission of image data during the interval where the low-power drive signal is at a logic high level, and The gate driver changes the pulse width of the gate signal among the plurality of gate signals that has a conduction level pulse that overlaps with the interval where the low-power drive signal is at a logic high level.

2. The display device according to claim 1, wherein, The gate driver includes: A level shifter is configured to generate a plurality of gate clock signals based on an on-clock signal and an off-clock signal included in the gate control signal; and A gate signal generator is configured to generate the plurality of gate signals based on the plurality of gate clock signals.

3. The display device according to claim 1, wherein, The gate driver reduces the pulse width of the gate signal among the plurality of gate signals that has a conduction level pulse that overlaps with the interval where the low-power drive signal is logic high.

4. The display device according to claim 3, wherein, The timing controller shifts the pulses in the multiple pulses included in the cutoff clock signal that overlap with the interval where the low-power drive signal is at a logic high level in the negative direction.

5. The display device according to claim 4, wherein, The falling edge of the gate signal among the plurality of gate signals, which has a falling edge corresponding to the pulse included in the cutoff clock signal and shifted in the negative direction, is shifted in the negative direction.

6. The display device according to claim 5, wherein, The rising edge of each of the plurality of gate signals is fixed.

7. The display device according to claim 4, wherein, The timing controller shifts the pulse width of each of the multiple pulses included in the cutoff clock signal that overlaps with the interval where the low-power drive signal is at a logic high level.

8. The display device according to claim 2, wherein, Each of the plurality of gate signals includes a gate pulse modulation period in which the signal level decreases stepwise or gradually at the falling edge, and The gate driver modulates the length of the gate pulse modulation period of the gate signal among the plurality of gate signals that has a conduction level pulse overlapping the interval where the low-power drive signal is logic high.

9. The display device according to claim 8, wherein, The timing controller increases the pulse width of the pulses in the multiple pulses included in the cutoff clock signal that overlap with the interval where the low-power drive signal is at a logic high level.

10. The display device according to claim 9, wherein, The timing controller shifts the rising edge of the pulse that overlaps with the interval where the low-power drive signal is at a logic high level in the multiple pulses included in the cutoff clock signal in the negative direction.

11. The display device according to claim 9, wherein, The gate pulse modulation period of the gate signal among the plurality of gate signals, which has a falling edge corresponding to the pulse included in the cutoff clock signal and having an increased pulse width, is increased.

12. The display device according to claim 9, wherein, The timing controller doubles the pulse width of the pulses in the multiple pulses included in the cutoff clock signal that overlap with the interval where the low-power drive signal is at a logic high level.

13. The display device according to claim 10, wherein, The timing controller shifts the rising edge of the pulses in the multiple pulses included in the cutoff clock signal that overlap with the interval where the low-power drive signal is at a logic high level by the pulse width of each pulse in the multiple pulses included in the cutoff clock signal.

14. The display device according to claim 1, wherein, The low-power drive signal has a high logic level corresponding to a horizontal time period of at least two pixel rows of an image displaying the same grayscale in a plurality of pixel rows of the display area.

15. The display device according to claim 8, wherein, The level shifter includes a backflip compensator that reduces the signal level in a stepwise or gradual manner at the falling edge.

16. The display device according to claim 10, wherein, The position of the falling edge of each of the plurality of gate signals is fixed.

17. A display device, comprising: A timing controller is configured to generate image data, data control signals, and gate control signals, the gate control signals including a cutoff clock signal; A data driver is configured to generate a plurality of data signals corresponding to the image data based on the data control signals; as well as A gate driver is configured to generate multiple gate signals based on an on-clock signal and an off-clock signal included in the gate control signal. Specifically, the timing controller stops the transmission of image data during the interval where the low-power drive signal is at a logic high level, and The timing controller modifies the pulse width of the pulses in the multiple pulses included in the cutoff clock signal that overlap with the interval where the low-power drive signal is at a logic high level.

18. The display device according to claim 17, wherein, The gate driver reduces the pulse width of the gate signal among the plurality of gate signals that has a conduction level pulse that overlaps with the interval where the low-power drive signal is at a logic high level.

19. The display device according to claim 18, wherein, The timing controller shifts the pulses in the multiple pulses included in the cutoff clock signal that overlap with the interval where the low-power drive signal is at a logic high level in the negative direction.

20. The display device according to claim 17, wherein, The timing controller increases the pulse width of the pulses in the multiple pulses included in the cutoff clock signal that overlap with the interval where the low-power drive signal is at a logic high level.

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