112 results about "Data transmission circuit" patented technology

An apparatus including a policy acquisition circuit structured to interpret a vehicle policy data value including vehicle status data; a policy processing circuit structured to generate parsed policy data that includes a vehicle data collection description; a policy execution circuit structured to collect vehicle data from one or more end points of at least one network zone of a vehicle; a vehicle data transmission circuit structured to transmit at least a portion of the collected vehicle data; and a vehicle status data adjustment circuit structured to interpret a vehicle status data collection change value.

The invention provides a UCIe standard protocol layer data transmission circuit, a related method and a chip, and the circuit comprises a slicing circuit which is configured to segment a data packet from a service port; sending the slice frame and slice description information associated with the slice frame to a framing device; the framing device is configured to fill a flow control unit Flit with the slice frames from the slice devices and slice description information associated with the slice frames, and send the Flit to the deframing device; the frame deframer is configured to determine slice frames belonging to the same service port from the Flit, and send the slice frames and slice description information associated with the slice frames to a packing circuit corresponding to the service port; and the packing circuit is configured to splice the data slices belonging to the same data packet in the slice frame based on the slice description information and output the data packet. The technical problem that extra delay is introduced due to beat insertion due to the fact that large multiplexers need to be introduced in existing protocol layer data transmission of the UCIe standard is solved.

The utility model discloses a multi-parameter laser photoelectric signal intelligent grading early warning device, which comprises a monitoring module provided with a laser power monitoring circuit, a wavelength monitoring circuit and a light spot quality monitoring circuit, a data acquisition and transmission module provided with a data acquisition circuit and a data transmission circuit, and a data processing module, the system is provided with a core processor circuit and a storage circuit, the grading early warning module is provided with a sound-light alarm circuit and a communication alarm circuit, and the user interaction module is provided with a display interface circuit and an operation control circuit. Therefore, multi-parameter monitoring, intelligent grading early warning and efficient data processing and interaction can be realized, the running state of the laser system can be comprehensively reflected, timely and accurate early warning can be realized, the monitoring efficiency is improved, the operation complexity is reduced, and safe and stable running of laser equipment is guaranteed.

The utility model provides a multi-interface charging test mainboard, which is applied to the field of charging test, and comprises a memory slot, a plurality of charging ports and a plurality of charging ports, the CPU slot is connected with the plurality of memory slots; a PCH chip, wherein the PCH chip is connected with the CPU slot; a Super I / O chip, wherein the Super I / O chip is connected with the PCH chip; the charging test circuit comprises a plurality of test interfaces, the input end of the charging test circuit is connected with the output end of the Super I / O chip, and the output end of the charging test circuit is connected with the PCH chip; the first input end of the data transmission circuit is connected with the PCH chip, the second input end of the data transmission circuit is connected with the output end of the Super I / O chip, and the output end of the data transmission circuit is connected with each test interface. The utility model aims to achieve the purpose of testing a plurality of USB PD devices in parallel.

The present disclosure relates to the field of semiconductor, and provides a memory for reducing power consumption of the memory without increasing memory area. The memory comprises a memory array, a data transmission circuit and a peripheral circuit; the data transmission circuit is arranged between the memory array and the peripheral circuit for data transmission between the memory array and the peripheral circuit; wherein the data transmission circuit comprises a first data path and a second data path in a data transmission direction; a power supply end of the first data path is electrically connected to a first transmission line, and a ground end is electrically connected to a second transmission line; a power supply end of the second data path is electrically connected to the second transmission line, and a ground end is electrically connected to a third transmission line; wherein the first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, the third transmission line is electrically connected to a common ground end, and the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.

A semiconductor memory device capable of improving the usage efficiency of a bus is provided. The semiconductor memory device includes a data storage unit, a data transfer circuit, and a control circuit. The data storage unit temporarily stores data read from a memory cell array. The data transfer circuit is provided between the data storage unit and an input / output pad, and transfers the data stored in the data storage unit to the input / output pad. When a predetermined time period elapses without the data transfer circuit starting data transfer to the memory controller through the input / output pad, the control circuit cuts off power supplied to the data transfer circuit. The predetermined time period can be changed according to an instruction from the memory controller.

The invention provides a data transmission circuit, a data receiving end, a data transmission method and a display device, belongs to the field of communication protocols, aims to improve the transmission efficiency of the data transmission circuit, is connected between a sending end and the receiving end, and comprises at least one pair of data lines configured to transmit electric signals corresponding to display data to be sent by the sending end; a pair of clock lines configured to provide a synchronous clock signal for an electrical signal transmitted on the data line; the first current flow direction sensor is connected between two data lines in the pair of data lines, is suitable for being connected with a receiving end, and is configured to provide a first current flow direction between the electric signals on the pair of data lines for the receiving end; and the second current flow direction sensor is connected between the at least one pair of data lines and one clock line in the pair of clock lines, is suitable for being connected with a receiving end, and is configured to provide a second current flow direction between the electric signals transmitted on the pair of data lines and one clock line for the receiving end.

The invention discloses an anti-radiation data transmission circuit, device and system, the anti-radiation data transmission circuit comprises a crystal oscillator oscillation starting circuit and a data transmission link, and the crystal oscillator oscillation starting circuit and the data transmission link are structurally enhanced by adopting an annular gate reinforcement technology; the crystal oscillator oscillation starting circuit comprises an external signal branch and an external crystal oscillator branch which are mutually backed up; and the data transmission link is used for converting the basic frequency signal output by the external signal branch or the external crystal oscillator branch into high-speed serial data and sending the high-speed serial data to the off-chip receiving module. According to the application, firstly, a redundant data source, namely an external signal branch and an external crystal oscillator branch which are mutually backed up, is provided, so that the data transmission reliability is improved, and meanwhile, the data reinforcement based on the annular gate is carried out on the first receiving module and the data transmission link, so that the reliability of data transmission is improved. And a high-stability data transmission link is constructed in combination with an external crystal oscillator with anti-radiation capability, so that the anti-radiation capability of the whole data transmission circuit is improved.

The utility model provides a non-contact data transmission circuit for a CT (Computed Tomography) machine, which comprises an optical signal-to-electric signal circuit, a radio-frequency signal transmitting circuit, a radio-frequency signal receiving circuit and an electric signal-to-optical signal circuit, and the input end of the optical signal-to-electric signal circuit can receive optical signals output by an optical signal output module of the CT machine. The output end of the optical signal-to-electric signal circuit is connected with the input end of the radio frequency signal transmitting circuit, the output end of the radio frequency signal transmitting circuit is in wireless communication connection with the input end of the radio frequency signal receiving circuit, and the output end of the radio frequency signal receiving circuit is connected with the input end of the electric signal-to-optical signal circuit. And the output end of the electric signal-to-optical signal circuit can be connected with the input end of a computer optical signal receiving module. The CT machine has the advantages that high-speed data transmission of the CT machine can be achieved, and optical signals are not prone to external interference.

The utility model relates to the technical field of motorcycle instruments, and particularly discloses a multifunctional motorcycle instrument panel which comprises an instrument panel shell, a display screen is installed on the instrument panel shell, and a PCB electrically connected with the display screen is arranged in the instrument panel shell. The PCB comprises a main control circuit, a power supply step-down circuit, a remote control receiving circuit, an audio power amplifier circuit, a key control circuit and a data transmission circuit, and the power supply step-down circuit, the remote control receiving circuit, the audio power amplifier circuit, the key control circuit and the data transmission circuit are all electrically connected with the main control circuit. The remote control receiving circuit is matched with the master control circuit to receive audio signals, and the audio signals are output after being amplified by the audio power amplifier circuit, so that the functions of playing music, a radio and the like are realized, the functions are diversified, the practicability is high, and the use requirements of users can be met.

The application discloses a kind of in-furnace temperature measuring device, temperature measuring method and computer readable storage medium, in-furnace temperature measuring device includes tray, connecting structure, power supply structure and multiple test batteries, each test battery is provided with multiple temperature measuring probes;Cavity is used to place test battery;Connecting structure includes temperature measuring instrument, temperature measuring instrument is connected with tray, temperature measuring instrument includes wireless receiving end and temperature measuring channel connected with temperature measuring probe, wireless transmitting end is connected with external device, external device is provided with wireless receiving end, wireless receiving end is matched with wireless transmitting end to switch on data transmission circuit, and data transmission circuit is used to transmit the temperature information of test battery;Power supply structure is connected with tray, and power supply structure is electrically connected with temperature measuring instrument.The application is switched on data transmission circuit by temperature measuring probe, wireless transmitting end and wireless receiving end cooperation, realizes the cavity station in single body furnace to carry out furnace temperature temperature test, avoids the installation wiring difficulty caused by wiring mode transmission data and so on.

The invention relates to the field of semiconductors, provides a memory, and aims to reduce the power consumption of the memory on the premise of not increasing the area of the memory. The memory comprises a memory array, a data transmission circuit and a peripheral circuit, the data transmission circuit is arranged between the storage array and the peripheral circuit and is used for data transmission between the storage array and the peripheral circuit; the data transmission circuit comprises a first data path and a second data path in the data transmission direction. The power end of the first data path is electrically connected with the first transmission line, and the grounding end is electrically connected with the second transmission line; the power end of the second data path is electrically connected with the second transmission line, and the grounding end is electrically connected with the third transmission line; wherein the first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, the third transmission line is electrically connected with the common grounding end, and the voltage value of the first power supply voltage is larger than that of the second power supply voltage.

The application provides a data transmission circuit and method based on signal conversion, a chip and an electronic device, and belongs to the field of circuits.The data transmission circuit based on signal conversion comprises a first conversion module and a second conversion module.The first conversion module is used for receiving a parallel signal from a first clock domain and converting the parallel signal into a serial signal of a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain.The second conversion module is used for receiving the serial signal and converting the serial signal into the parallel signal.The scheme realizes the transmission of the parallel signal from the first conversion module to the second conversion module within a first clock cycle.By applying the data transmission circuit based on signal conversion to transmit signals between FPGAs, a large number of signals can be transmitted from one FPGA to another FPGA within a clock cycle, thereby reducing the difficulty of circuit design and timing convergence.

Provided are a data transmission circuit system and a data reception circuit system, which use an edge of a pulse signal. The data transmission circuit system modulates a digital signal by using time levels determined based on time differences between rising edges and falling edges of a clock pulse signal, and rising edges and falling edges of a data pulse signal. The data reception circuit system demodulates a digital signal by using time levels determined based on time differences between rising edges and falling edges of a recovered clock pulse signal, and rising edges and falling edges of a data pulse signal.

The application provides a UCIe standard protocol layer data transmission circuit, a related method and a chip. The circuit comprises: a slicing circuit configured to split data packets from a service port; a framing device configured to send a slice frame and slice description information associated with the slice frame to a framing device; the framing device is configured to fill the slice frame and the slice description information associated with each slice frame from each slicer into a flow control unit Flit, and send the Flit to a deframer; the deframer is configured to determine the slice frame belonging to the same service port from the Flit, and send the slice frame and the slice description information associated with the slice frame to the packet assembly circuit corresponding to the service port; the packet assembly circuit is configured to splice and output the data packets in the slice frame based on the slice description information. The existing UCIe standard protocol layer data transmission needs to introduce a large multiplexer, which causes a technical problem of inserting a snapshot and introducing additional delay.

A touch microcontroller unit including a touch data acquisition circuit to acquire touch data of a first area and a second area of a first panel. The touch microcontroller unit including an area division boundary calculation circuit to calculate a boundary in the first panel to divide the first area and the second area. The touch microcontroller unit including a touch coordinate calculation circuit to calculate touch coordinates of the first area based on the touch data of the first area. The touch microcontroller unit including a touch data transmission circuit to transmit the touch coordinates of the first area and the touch data of the second area to another touch microcontroller unit.

The utility model discloses an on-chain identity identification label device for bicycle traceability. The on-chain identity identification tag device comprises a main controller embedded in a bicycle body, a near field communication (NFC) chip, an anti-disassembly detection circuit, a data transmission circuit, a power management module, a sensor combination, a crystal oscillator, an analog-to-digital converter, a display screen and a two-dimensional code display layer, wherein the main controller is respectively connected with the NFC communication chip, the anti-tamper detection circuit, the data transmission circuit, the power management module, the sensor combination, the crystal oscillator, the analog-to-digital converter, the display screen and the two-dimensional code display layer, and the NFC communication chip is respectively connected with the anti-tamper detection circuit, the sensor combination, the crystal oscillator and the data transmission circuit. And the sensor combination is respectively connected with the data transmission circuit and the analog-to-digital converter. According to the utility model, the tamper-proof detection of the bicycle label is realized, and the integrated target of tamper-proof and hardware binding is realized on the physical structure.

A memory device and an operating method thereof are provided. The memory device includes: a latch configured to sense a voltage or current of a bit line coupled to a memory cell and store read data; a transmission circuit configured to output the read data stored in the latch via a page bus in response to a transmission signal; a cache latch configured to receive the read data via the page bus and temporarily store the read data; and a pump voltage output circuit coupled to the transmission circuit via a transmission line and configured to apply a second voltage greater than the first voltage after applying a first voltage to the transmission line for a set time.

Techniques are described for efficiently and reliably managing machine check exceptions. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions; a plurality of machine check architecture (MCA) banks coupled to the plurality of cores, each MCA bank comprising a plurality of MCA registers to store machine check data (MCD); MCD transmission circuitry to transmit a packet to an error monitoring server, the MCD transmission circuitry to generate a header of the packet using header information stored in one or more packet configuration registers and to generate a payload of the packet using at least a portion of the MCD stored in one or more of the MCA registers.

To provide a semiconductor storage device that can improve bus utilization efficiency.SOLUTION: A semiconductor storage device includes a data holding part, a data transfer circuit, and a control part. The data holding part temporarily holds data read from a memory cell array. The data transfer circuit is provided between the data holding part and a pad part and transfers the data held in the data holding part to an input / output pad. The data transfer circuit is provided with a blocking part capable of blocking a current supply to the data transfer circuit. When a predetermined time has elapsed without data transfer to a memory controller after the data has been transferred to the data transfer circuit from the memory cell array via the data holding part, the control part blocks the current supply to the data transfer circuit by means of the blocking part. The predetermined time is changeable.SELECTED DRAWING: Figure 2

A data transmission circuit and method, a core, a multi-core chip, an electronic device, and a storage medium are disclosed. The data transmission circuit includes a receiving unit, a control unit, a lookup table unit, and a selection unit. The receiving unit receives original data packets from Fabric. The control unit determines whether the original data packet needs relaying based on an original control bit. In response to the need for relaying, the control unit activates a first input terminal of the selection unit, which then sends a new data packet to Fabric via the first input terminal. The new data packet includes the original data and a new header obtained by the lookup table unit based on the original index. This data transmission circuit effectively reduces power consumption during data transmission between multiple cores.

A data transmission circuit is improved to support a data transmission mode suitable for an interface or an application according to selection of an option. The data transmission circuit includes a pre-driver configured to output a first differential drive signal, a second differential drive signal, and a pre-emphasis control signal by using a first differential data signal, a second differential data signal, and an option signal; a main driver configured to output a first differential transmission signal and a second differential transmission signal by using the first differential drive signal and the second differential drive signal; and a pre-emphasis driver configured to perform pre-emphasis of different amplification degrees on the first differential transmission signal and the second differential transmission signal in a first mode and a second mode by the pre-emphasis control signal.

An embodiment of the present disclosure provides a data transmission circuit and a memory. The data transmission circuit includes a calibration circuit and an output circuit. The calibration circuit is connected to the output circuit and is used to adjust the impedance of the output circuit. The calibration circuit includes: a calibration control circuit for generating and outputting a calibration code; a calibration unit including multiple groups of first transistors and second transistors connected in series; the gate of the first transistor is connected to the calibration control circuit and is used to receive the calibration code; the calibration control circuit is also used to control the conduction or cutoff of the multiple first transistors through the calibration code to adjust the resistance value of the calibration unit to a standard resistance value; when the first transistor is turned on, the first operating voltage on the gate is less than the second operating voltage on the gate when the second transistor is turned on.

The invention relates to a method and an apparatus for controlling an output resistance of a data transmitter. The present description relates to a data transmission circuit comprising: an output branch comprising a first resistor, a first transistor and a second transistor connected in series between a first voltage rail and a first output node, the second transistor being configured to receive a data signal on a gate thereof; a replica branch of the output branch between the first voltage rail and the second node; a current source coupled to the second node and a second voltage rail; and a voltage control circuit configured to control the gate voltage.

A data transmission circuit, a data transmission method and an electronic device are provided. The data transmission circuit includes a data processing circuit and a data driving circuit. The data processing circuit is configured to receive a first data signal in a parallel state and convert the first data signal into a second data signal in a serial state. The data driving circuit includes a driving main circuit and a driving regulation circuit. The driving regulation circuit is configured to reduce, in response to the driving regulation circuit being in an enabled state, a voltage difference of the second data signal, to shorten a charging and discharging time and implement driving enhancement. The driving main circuit is configured to perform driving on an enhanced second data signal to obtain a target transmission signal.

The utility model discloses an aviation oil power distribution air switch state monitoring device comprising a plurality of monitoring branches which are connected in parallel to form a monitoring circuit. The monitoring circuit and the data transmission circuit form a loop; the monitoring branch is provided with a photoelectric signal isolator, and one end of the photoelectric signal isolator is connected with a live wire end of an air switch of the aviation oil power distribution equipment; the other ends of the plurality of photoelectric signal isolators are integrated together and are jointly connected with a zero line of the power distribution cabinet; the data transmission circuit is connected in series with a data transmission chip, a data processor and a power supply chip; the data transmission circuit is provided with a power supply positive terminal and a power supply negative terminal, and the power supply positive terminal is connected with the power supply chip; the power supply positive terminal and the power supply negative terminal are respectively connected with a positive electrode and a negative electrode of an external power supply. According to the utility model, the state of the aviation oil distribution air switch can be monitored in real time.

The embodiment of the present disclosure provides a current accumulator, a data transmission circuit and a semiconductor device. The current accumulator comprises: a switch tube connected between a feedback node and a ground terminal; and an inverter, an input end of the inverter receiving a feedback signal, and an output end of the inverter being connected to a control end of the switch tube, the switch tube being turned on or turned off in response to a level of the control end, so as to turn on or turn off between the feedback node and the ground terminal, thereby adjusting the level of the feedback node. The embodiment of the present disclosure is beneficial to improving the response rate of the current accumulator.

A regenerative limiting circuit for potentially explosive areas, for supplying energy to a sensor and for data communication with a sensor, has an input unit, a first limiting unit, a second limiting unit, a monitoring unit, a high-voltage unit, a node unit, and a reference potential. The input unit has first and second data line connections, a supply line connection, and a zero line connection, each for connecting a connection cable. The first limiting unit is connected to the first data line connection, the second limiting unit is connected to the second data line connection and has a resistor and a Zener diode, wherein the Zener diode connects through to the reference potential in each case in the event of an overvoltage. The monitoring unit is connected to the first limiting unit and the second limiting unit, and is suitable for evaluating data.

The present description concerns a data transmission circuit comprising an output branch comprising a first resistor, a first transistor, and a second transistor series-connected between a first voltage rail and a first output node, the second transistor being configured to receive on its gate a data signal; a branch of duplication of the output branch, between the first voltage rail and a second node; a current source coupling the second node and a second voltage rail; and a voltage control circuit configured to control a gate voltage.

The invention discloses a wireless charging system. Relates to the wireless energy and signal simultaneous transmission field, and comprises an energy transmission circuit comprising an energy transmitting circuit, a coupler and an energy receiving circuit, the coupler comprises an energy transmitting coil and an energy receiving coil, the energy transmitting coil is used for coupling electromagnetic energy received from the energy transmitting circuit to the energy receiving coil, and the energy receiving coil is used for receiving the electromagnetic energy; the energy receiving coil is used for transmitting the electromagnetic energy to the energy receiving circuit, and the energy receiving circuit is used for wirelessly charging target equipment according to the electromagnetic energy; the data transmission circuit comprises a data transmitting circuit, a coupler and a data receiving circuit, the coupler further comprises a data transmitting coil and a data receiving coil, the data transmitting coil is used for coupling data signals received from the data transmitting circuit to the data receiving coil, and the data receiving coil is used for transmitting the data signals to the data receiving circuit. The data receiving circuit is used for determining the charging state of the target equipment according to the data signal.