202 results about "Data transmission circuit" patented technology

Provided are a data transmission circuit system and a data reception circuit system, which use an edge of a pulse signal. The data transmission circuit system modulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a clock pulse signal and rising edges (or falling edges) of a data pulse signal. The data reception circuit system demodulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a recovered clock pulse signal and rising edges (or falling edges) of a data pulse signal.

An apparatus including a policy acquisition circuit structured to interpret a vehicle policy data value including vehicle status data; a policy processing circuit structured to generate parsed policy data that includes a vehicle data collection description; a policy execution circuit structured to collect vehicle data from one or more end points of at least one network zone of a vehicle; a vehicle data transmission circuit structured to transmit at least a portion of the collected vehicle data; and a vehicle status data adjustment circuit structured to interpret a vehicle status data collection change value.

This application discloses a data transmission circuit, a data transmission method, and an electronic device. The data transmission circuit includes a storage chip, a data transit chip, and a data processing chip. The storage chip, the data transit chip, and the data processing chip are sequentially connected in series. The data transit chip is configured to read a first data packet with a first preset quantity of bits from the storage chip, process the first data packet into a plurality of second data packets each with a second preset quantity of bits, and send the second data packets to the data processing chip. A maximum quantity of bits of a data packet that the data processing chip is able to read at a time is a third preset quantity of bits.

A data transfer circuit in a nonvolatile memory device includes first repeaters, second repeaters and signal lines. The signal lines connect the first repeaters and the second repeaters, and include a first group of signal lines and a second group of signal lines alternatingly arranged. The first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters include a third group of repeaters activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines floated in the second operation mode, and a fourth group of repeaters activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines floated in the first operation mode.

The invention provides a UCIe standard protocol layer data transmission circuit, a related method and a chip, and the circuit comprises a slicing circuit which is configured to segment a data packet from a service port; sending the slice frame and slice description information associated with the slice frame to a framing device; the framing device is configured to fill a flow control unit Flit with the slice frames from the slice devices and slice description information associated with the slice frames, and send the Flit to the deframing device; the frame deframer is configured to determine slice frames belonging to the same service port from the Flit, and send the slice frames and slice description information associated with the slice frames to a packing circuit corresponding to the service port; and the packing circuit is configured to splice the data slices belonging to the same data packet in the slice frame based on the slice description information and output the data packet. The technical problem that extra delay is introduced due to beat insertion due to the fact that large multiplexers need to be introduced in existing protocol layer data transmission of the UCIe standard is solved.

A data transmission circuit including: an encoder configured to output a transition signal that indicates a transition state of an input data signal; a first serializer that receives the transition signal; an auxiliary driver configured to receive an output of the first serializer and drive an output node; a second serializer that receives the input data signal; and a main driver configured to receive an output of the second serializer and drive the output node.

A system including circuitry to communicate data across an isolation barrier of a switch driver circuit. For switch driver circuits with galvanic isolation, the circuitry of this disclosure uses the unavoidable common mode voltages caused by the coupling capacitances of the data transfer circuit to evaluate the common mode voltage characteristics, such as the slew rate of a switching event. The switch driver circuit of this disclosure may include a common mode voltage detector to detect and measure features of the unavoidable common mode voltage during a switching event, such as voltage amplitude and slew rate. The common mode voltage detector may couple to a communication interface that provides the common mode voltage information to a controller for the switch driver circuit. In some examples, based on the received information, the controller may adjust the operation of the switching circuit.

The present application relates to a data transmission circuit, method and storage device, wherein the data transmission circuit includes a comparison module, a data conversion module and a read-write conversion circuit, wherein the comparison module is used to compare the first data on the received data bus with the second data on the global data line, and output a comparison result of whether the number of bits that are different between the first data and the second data exceeds a preset threshold; the data conversion module is used to invert the first data and transmit it to the global data line if the comparison result exceeds the preset threshold, and transmit the first data to the global data line if the comparison result does not exceed the preset threshold; the read-write conversion circuit is used to transmit the data on the global data line to the complementary local data line if the comparison result exceeds the preset threshold, and transmit the data on the global data line to the local data line if the comparison result does not exceed the preset threshold. The present application effectively reduces the power consumption during data transmission.

Circuits, devices, and systems incorporating a low-voltage common-mode transient immunity (CMTI) test. The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common-mode transient rejection, the first signal path should be the same as the second signal path. Differences in resistance, inductance, and capacitance between the two signal paths may result in common-mode noise being measured at the output terminals as a differential signal. Devices according to the techniques of this disclosure are configured to include a test mode to perform a low-voltage test that outputs a measurement of the CMTI at any stage of production or field deployment.

Circuits, devices and systems that include a low voltage test for common mode transient immunity (CMTI). The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common mode transient rejection, the first signal path should be the same as the second signal path. Differences in the resistance, inductance, and capacitance between the two signal paths may result in common mode noise being measured as a differential signal at the output terminals. Devices according to the techniques of this disclosure are configured to enter a test mode to conduct a low voltage test that outputs a measurement of CMTI at any phase of production or field use.

The present application provides an eMMC chip test system and a power-on and power-off test method, which are applied to the technical field of storage chip security test. The eMMC test system is composed of an XU4 platform and an eMMC chip test platform. The XU4 platform includes a data transmission circuit, a storage device, an XU4 main control chip, a first signal transmission interface, a power module and a first power interface. The XU4 main control chip is connected to the first signal transmission interface, and the power module is connected to the first power interface; the eMMC chip test platform includes a second power interface, a second signal transmission interface, a voltage conversion module and a test chip circuit. The second power interface is connected to the voltage conversion module. The voltage conversion module has a first output end and a second output end, both of which are connected to the test chip circuit, and the second signal transmission interface is connected to the test chip circuit. The power state of the eMMC chip when it is accidentally or intentionally powered on or off at any time can be simulated to achieve the test of the impact of all power-on and power-off conditions of the eMMC on data transmission.

The utility model discloses a multi-parameter laser photoelectric signal intelligent grading early warning device, which comprises a monitoring module provided with a laser power monitoring circuit, a wavelength monitoring circuit and a light spot quality monitoring circuit, a data acquisition and transmission module provided with a data acquisition circuit and a data transmission circuit, and a data processing module, the system is provided with a core processor circuit and a storage circuit, the grading early warning module is provided with a sound-light alarm circuit and a communication alarm circuit, and the user interaction module is provided with a display interface circuit and an operation control circuit. Therefore, multi-parameter monitoring, intelligent grading early warning and efficient data processing and interaction can be realized, the running state of the laser system can be comprehensively reflected, timely and accurate early warning can be realized, the monitoring efficiency is improved, the operation complexity is reduced, and safe and stable running of laser equipment is guaranteed.

The utility model provides a multi-interface charging test mainboard, which is applied to the field of charging test, and comprises a memory slot, a plurality of charging ports and a plurality of charging ports, the CPU slot is connected with the plurality of memory slots; a PCH chip, wherein the PCH chip is connected with the CPU slot; a Super I / O chip, wherein the Super I / O chip is connected with the PCH chip; the charging test circuit comprises a plurality of test interfaces, the input end of the charging test circuit is connected with the output end of the Super I / O chip, and the output end of the charging test circuit is connected with the PCH chip; the first input end of the data transmission circuit is connected with the PCH chip, the second input end of the data transmission circuit is connected with the output end of the Super I / O chip, and the output end of the data transmission circuit is connected with each test interface. The utility model aims to achieve the purpose of testing a plurality of USB PD devices in parallel.

The present invention provides a data transmission circuit and an image sensor, wherein the data transmission circuit comprises: a first data transmission module and a second data transmission module, wherein the first data transmission module comprises at least one data transmission unit; the data transmission unit comprises a data transmission line and a driving unit, wherein the driving unit is connected to the output end of the same counting position of all the counters in the image sensor through the data transmission line; the driving unit obtains the output of the counting position through the data transmission line, converts the output of the counting position into a current difference inside the driving unit, and converts the current difference into a voltage difference. The driving unit in the data transmission circuit provided by the present invention can quickly convert the output of the counting position into a current difference inside the driving unit, and immediately amplify and output, which can meet the requirements of high-resolution and high-frame-rate data transmission of the image sensor.

The present disclosure relates to the field of semiconductor, and provides a memory for reducing power consumption of the memory without increasing memory area. The memory comprises a memory array, a data transmission circuit and a peripheral circuit; the data transmission circuit is arranged between the memory array and the peripheral circuit for data transmission between the memory array and the peripheral circuit; wherein the data transmission circuit comprises a first data path and a second data path in a data transmission direction; a power supply end of the first data path is electrically connected to a first transmission line, and a ground end is electrically connected to a second transmission line; a power supply end of the second data path is electrically connected to the second transmission line, and a ground end is electrically connected to a third transmission line; wherein the first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, the third transmission line is electrically connected to a common ground end, and the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.

A semiconductor memory device capable of improving the usage efficiency of a bus is provided. The semiconductor memory device includes a data storage unit, a data transfer circuit, and a control circuit. The data storage unit temporarily stores data read from a memory cell array. The data transfer circuit is provided between the data storage unit and an input / output pad, and transfers the data stored in the data storage unit to the input / output pad. When a predetermined time period elapses without the data transfer circuit starting data transfer to the memory controller through the input / output pad, the control circuit cuts off power supplied to the data transfer circuit. The predetermined time period can be changed according to an instruction from the memory controller.

Examples of the present application disclose a page buffer including a plurality of latch circuits. Each latch circuit includes a resetting control circuit, a setting control circuit, a data transmission circuit, and a latch transmission circuit. The resetting control circuit is coupled to a first data node and configured to receive a first supply voltage, so as to determine a potential of the first data node. The setting control circuit is coupled to a second data node and configured to receive the first supply voltage, so as to determine a potential of the second data node. The data transmission circuit is coupled to the first data node and the second data node and configured to receive a second supply voltage. The latch transmission circuit is coupled to the first data node, the second data node, and a sense node. The first supply voltage is higher than the second supply voltage.

The invention provides a data transmission circuit, a data receiving end, a data transmission method and a display device, belongs to the field of communication protocols, aims to improve the transmission efficiency of the data transmission circuit, is connected between a sending end and the receiving end, and comprises at least one pair of data lines configured to transmit electric signals corresponding to display data to be sent by the sending end; a pair of clock lines configured to provide a synchronous clock signal for an electrical signal transmitted on the data line; the first current flow direction sensor is connected between two data lines in the pair of data lines, is suitable for being connected with a receiving end, and is configured to provide a first current flow direction between the electric signals on the pair of data lines for the receiving end; and the second current flow direction sensor is connected between the at least one pair of data lines and one clock line in the pair of clock lines, is suitable for being connected with a receiving end, and is configured to provide a second current flow direction between the electric signals transmitted on the pair of data lines and one clock line for the receiving end.

The disclosed data transmission circuit and a memory include a sense amplifier circuit, a first sub-discharge path, a second sub-discharge path, and a discharge adjustment unit. The sense amplifier circuit generate amplified signals based on two terminals. The first sub-discharge path, in the read state, discharges at the first terminal to the discharge terminal based on the first data line signal; the second sub-discharge path, in reading state, discharges at the second terminal to the discharge terminal based on the discharge adjustment signa. The discharge adjustment unit is electrically connected to the second sub-discharge path and the control signal, but is not connected to the first sub-discharge path, and is used for generating the discharge adjustment signal based on the control signal, to adjust the discharge capacity of the second sub-discharge path. The present disclosure improves the anti-interference ability and data transmission efficiency of the data transmission circuit.

The invention discloses an anti-radiation data transmission circuit, device and system, the anti-radiation data transmission circuit comprises a crystal oscillator oscillation starting circuit and a data transmission link, and the crystal oscillator oscillation starting circuit and the data transmission link are structurally enhanced by adopting an annular gate reinforcement technology; the crystal oscillator oscillation starting circuit comprises an external signal branch and an external crystal oscillator branch which are mutually backed up; and the data transmission link is used for converting the basic frequency signal output by the external signal branch or the external crystal oscillator branch into high-speed serial data and sending the high-speed serial data to the off-chip receiving module. According to the application, firstly, a redundant data source, namely an external signal branch and an external crystal oscillator branch which are mutually backed up, is provided, so that the data transmission reliability is improved, and meanwhile, the data reinforcement based on the annular gate is carried out on the first receiving module and the data transmission link, so that the reliability of data transmission is improved. And a high-stability data transmission link is constructed in combination with an external crystal oscillator with anti-radiation capability, so that the anti-radiation capability of the whole data transmission circuit is improved.

The utility model provides a non-contact data transmission circuit for a CT (Computed Tomography) machine, which comprises an optical signal-to-electric signal circuit, a radio-frequency signal transmitting circuit, a radio-frequency signal receiving circuit and an electric signal-to-optical signal circuit, and the input end of the optical signal-to-electric signal circuit can receive optical signals output by an optical signal output module of the CT machine. The output end of the optical signal-to-electric signal circuit is connected with the input end of the radio frequency signal transmitting circuit, the output end of the radio frequency signal transmitting circuit is in wireless communication connection with the input end of the radio frequency signal receiving circuit, and the output end of the radio frequency signal receiving circuit is connected with the input end of the electric signal-to-optical signal circuit. And the output end of the electric signal-to-optical signal circuit can be connected with the input end of a computer optical signal receiving module. The CT machine has the advantages that high-speed data transmission of the CT machine can be achieved, and optical signals are not prone to external interference.

The utility model relates to the technical field of motorcycle instruments, and particularly discloses a multifunctional motorcycle instrument panel which comprises an instrument panel shell, a display screen is installed on the instrument panel shell, and a PCB electrically connected with the display screen is arranged in the instrument panel shell. The PCB comprises a main control circuit, a power supply step-down circuit, a remote control receiving circuit, an audio power amplifier circuit, a key control circuit and a data transmission circuit, and the power supply step-down circuit, the remote control receiving circuit, the audio power amplifier circuit, the key control circuit and the data transmission circuit are all electrically connected with the main control circuit. The remote control receiving circuit is matched with the master control circuit to receive audio signals, and the audio signals are output after being amplified by the audio power amplifier circuit, so that the functions of playing music, a radio and the like are realized, the functions are diversified, the practicability is high, and the use requirements of users can be met.

The application discloses a kind of in-furnace temperature measuring device, temperature measuring method and computer readable storage medium, in-furnace temperature measuring device includes tray, connecting structure, power supply structure and multiple test batteries, each test battery is provided with multiple temperature measuring probes;Cavity is used to place test battery;Connecting structure includes temperature measuring instrument, temperature measuring instrument is connected with tray, temperature measuring instrument includes wireless receiving end and temperature measuring channel connected with temperature measuring probe, wireless transmitting end is connected with external device, external device is provided with wireless receiving end, wireless receiving end is matched with wireless transmitting end to switch on data transmission circuit, and data transmission circuit is used to transmit the temperature information of test battery;Power supply structure is connected with tray, and power supply structure is electrically connected with temperature measuring instrument.The application is switched on data transmission circuit by temperature measuring probe, wireless transmitting end and wireless receiving end cooperation, realizes the cavity station in single body furnace to carry out furnace temperature temperature test, avoids the installation wiring difficulty caused by wiring mode transmission data and so on.

The invention relates to the field of semiconductors, provides a memory, and aims to reduce the power consumption of the memory on the premise of not increasing the area of the memory. The memory comprises a memory array, a data transmission circuit and a peripheral circuit, the data transmission circuit is arranged between the storage array and the peripheral circuit and is used for data transmission between the storage array and the peripheral circuit; the data transmission circuit comprises a first data path and a second data path in the data transmission direction. The power end of the first data path is electrically connected with the first transmission line, and the grounding end is electrically connected with the second transmission line; the power end of the second data path is electrically connected with the second transmission line, and the grounding end is electrically connected with the third transmission line; wherein the first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, the third transmission line is electrically connected with the common grounding end, and the voltage value of the first power supply voltage is larger than that of the second power supply voltage.

The application provides a data transmission circuit and method based on signal conversion, a chip and an electronic device, and belongs to the field of circuits.The data transmission circuit based on signal conversion comprises a first conversion module and a second conversion module.The first conversion module is used for receiving a parallel signal from a first clock domain and converting the parallel signal into a serial signal of a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain.The second conversion module is used for receiving the serial signal and converting the serial signal into the parallel signal.The scheme realizes the transmission of the parallel signal from the first conversion module to the second conversion module within a first clock cycle.By applying the data transmission circuit based on signal conversion to transmit signals between FPGAs, a large number of signals can be transmitted from one FPGA to another FPGA within a clock cycle, thereby reducing the difficulty of circuit design and timing convergence.

Provided are a data transmission circuit system and a data reception circuit system, which use an edge of a pulse signal. The data transmission circuit system modulates a digital signal by using time levels determined based on time differences between rising edges and falling edges of a clock pulse signal, and rising edges and falling edges of a data pulse signal. The data reception circuit system demodulates a digital signal by using time levels determined based on time differences between rising edges and falling edges of a recovered clock pulse signal, and rising edges and falling edges of a data pulse signal.

The application provides a UCIe standard protocol layer data transmission circuit, a related method and a chip. The circuit comprises: a slicing circuit configured to split data packets from a service port; a framing device configured to send a slice frame and slice description information associated with the slice frame to a framing device; the framing device is configured to fill the slice frame and the slice description information associated with each slice frame from each slicer into a flow control unit Flit, and send the Flit to a deframer; the deframer is configured to determine the slice frame belonging to the same service port from the Flit, and send the slice frame and the slice description information associated with the slice frame to the packet assembly circuit corresponding to the service port; the packet assembly circuit is configured to splice and output the data packets in the slice frame based on the slice description information. The existing UCIe standard protocol layer data transmission needs to introduce a large multiplexer, which causes a technical problem of inserting a snapshot and introducing additional delay.

A touch microcontroller unit including a touch data acquisition circuit to acquire touch data of a first area and a second area of a first panel. The touch microcontroller unit including an area division boundary calculation circuit to calculate a boundary in the first panel to divide the first area and the second area. The touch microcontroller unit including a touch coordinate calculation circuit to calculate touch coordinates of the first area based on the touch data of the first area. The touch microcontroller unit including a touch data transmission circuit to transmit the touch coordinates of the first area and the touch data of the second area to another touch microcontroller unit.

The utility model discloses a differential IIC data transmission circuit for a low-speed vehicle, and the circuit comprises a bidirectional data buffer circuit which is used for obtaining a signal and uploading the signal to a differential conversion output circuit; the differential conversion output circuit is used for performing differential signal transmission on the signal; the differential conversion output circuit comprises a chip U2, a chip U3, a resistor R7, a resistor R8, a resistor R9 and a resistor R10, pins 5 and 8 of the chip U2 are connected with the resistor R7, pins 7 and 6 of the chip U2 are connected with the resistor R8, pins 5 and 8 of the chip U3 are connected with the resistor R9, and pins 7 and 6 of the chip U2 are connected with the resistor R10. According to the differential IIC data transmission circuit of the low-speed vehicle, the 485 transceiver is used for expanding the I2C range from onboard to non-onboard through the transmission cable, then signals are converted back to the I2C, the data transmission distance of the IIC is prolonged, and compared with an I2C line expanded only through an I2C buffer, the differential signals can improve EMI suppression, reduce power consumption and reduce the problem of different grounding potentials between circuit boards. And in a noisy environment in which EMI factors need to be considered, the anti-interference capability is improved.

The utility model discloses an on-chain identity identification label device for bicycle traceability. The on-chain identity identification tag device comprises a main controller embedded in a bicycle body, a near field communication (NFC) chip, an anti-disassembly detection circuit, a data transmission circuit, a power management module, a sensor combination, a crystal oscillator, an analog-to-digital converter, a display screen and a two-dimensional code display layer, wherein the main controller is respectively connected with the NFC communication chip, the anti-tamper detection circuit, the data transmission circuit, the power management module, the sensor combination, the crystal oscillator, the analog-to-digital converter, the display screen and the two-dimensional code display layer, and the NFC communication chip is respectively connected with the anti-tamper detection circuit, the sensor combination, the crystal oscillator and the data transmission circuit. And the sensor combination is respectively connected with the data transmission circuit and the analog-to-digital converter. According to the utility model, the tamper-proof detection of the bicycle label is realized, and the integrated target of tamper-proof and hardware binding is realized on the physical structure.