148 results about "Data transmission circuit" patented technology

Provided are a data transmission circuit system and a data reception circuit system, which use an edge of a pulse signal. The data transmission circuit system modulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a clock pulse signal and rising edges (or falling edges) of a data pulse signal. The data reception circuit system demodulates a digital signal by using time levels determined by time differences between rising edges (or falling edges) of a recovered clock pulse signal and rising edges (or falling edges) of a data pulse signal.

An apparatus including a policy acquisition circuit structured to interpret a vehicle policy data value including vehicle status data; a policy processing circuit structured to generate parsed policy data that includes a vehicle data collection description; a policy execution circuit structured to collect vehicle data from one or more end points of at least one network zone of a vehicle; a vehicle data transmission circuit structured to transmit at least a portion of the collected vehicle data; and a vehicle status data adjustment circuit structured to interpret a vehicle status data collection change value.

The invention provides a UCIe standard protocol layer data transmission circuit, a related method and a chip, and the circuit comprises a slicing circuit which is configured to segment a data packet from a service port; sending the slice frame and slice description information associated with the slice frame to a framing device; the framing device is configured to fill a flow control unit Flit with the slice frames from the slice devices and slice description information associated with the slice frames, and send the Flit to the deframing device; the frame deframer is configured to determine slice frames belonging to the same service port from the Flit, and send the slice frames and slice description information associated with the slice frames to a packing circuit corresponding to the service port; and the packing circuit is configured to splice the data slices belonging to the same data packet in the slice frame based on the slice description information and output the data packet. The technical problem that extra delay is introduced due to beat insertion due to the fact that large multiplexers need to be introduced in existing protocol layer data transmission of the UCIe standard is solved.

Circuits, devices, and systems incorporating a low-voltage common-mode transient immunity (CMTI) test. The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common-mode transient rejection, the first signal path should be the same as the second signal path. Differences in resistance, inductance, and capacitance between the two signal paths may result in common-mode noise being measured at the output terminals as a differential signal. Devices according to the techniques of this disclosure are configured to include a test mode to perform a low-voltage test that outputs a measurement of the CMTI at any stage of production or field deployment.

Circuits, devices and systems that include a low voltage test for common mode transient immunity (CMTI). The CMTI test of this disclosure may be used in a variety of applications, such as a data transmission circuit configured to communicate across galvanic isolation. A differential circuit may include two signal paths. For robust common mode transient rejection, the first signal path should be the same as the second signal path. Differences in the resistance, inductance, and capacitance between the two signal paths may result in common mode noise being measured as a differential signal at the output terminals. Devices according to the techniques of this disclosure are configured to enter a test mode to conduct a low voltage test that outputs a measurement of CMTI at any phase of production or field use.

The utility model discloses a multi-parameter laser photoelectric signal intelligent grading early warning device, which comprises a monitoring module provided with a laser power monitoring circuit, a wavelength monitoring circuit and a light spot quality monitoring circuit, a data acquisition and transmission module provided with a data acquisition circuit and a data transmission circuit, and a data processing module, the system is provided with a core processor circuit and a storage circuit, the grading early warning module is provided with a sound-light alarm circuit and a communication alarm circuit, and the user interaction module is provided with a display interface circuit and an operation control circuit. Therefore, multi-parameter monitoring, intelligent grading early warning and efficient data processing and interaction can be realized, the running state of the laser system can be comprehensively reflected, timely and accurate early warning can be realized, the monitoring efficiency is improved, the operation complexity is reduced, and safe and stable running of laser equipment is guaranteed.

The utility model provides a multi-interface charging test mainboard, which is applied to the field of charging test, and comprises a memory slot, a plurality of charging ports and a plurality of charging ports, the CPU slot is connected with the plurality of memory slots; a PCH chip, wherein the PCH chip is connected with the CPU slot; a Super I / O chip, wherein the Super I / O chip is connected with the PCH chip; the charging test circuit comprises a plurality of test interfaces, the input end of the charging test circuit is connected with the output end of the Super I / O chip, and the output end of the charging test circuit is connected with the PCH chip; the first input end of the data transmission circuit is connected with the PCH chip, the second input end of the data transmission circuit is connected with the output end of the Super I / O chip, and the output end of the data transmission circuit is connected with each test interface. The utility model aims to achieve the purpose of testing a plurality of USB PD devices in parallel.

The present disclosure relates to the field of semiconductor, and provides a memory for reducing power consumption of the memory without increasing memory area. The memory comprises a memory array, a data transmission circuit and a peripheral circuit; the data transmission circuit is arranged between the memory array and the peripheral circuit for data transmission between the memory array and the peripheral circuit; wherein the data transmission circuit comprises a first data path and a second data path in a data transmission direction; a power supply end of the first data path is electrically connected to a first transmission line, and a ground end is electrically connected to a second transmission line; a power supply end of the second data path is electrically connected to the second transmission line, and a ground end is electrically connected to a third transmission line; wherein the first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, the third transmission line is electrically connected to a common ground end, and the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.

A semiconductor memory device capable of improving the usage efficiency of a bus is provided. The semiconductor memory device includes a data storage unit, a data transfer circuit, and a control circuit. The data storage unit temporarily stores data read from a memory cell array. The data transfer circuit is provided between the data storage unit and an input / output pad, and transfers the data stored in the data storage unit to the input / output pad. When a predetermined time period elapses without the data transfer circuit starting data transfer to the memory controller through the input / output pad, the control circuit cuts off power supplied to the data transfer circuit. The predetermined time period can be changed according to an instruction from the memory controller.

Examples of the present application disclose a page buffer including a plurality of latch circuits. Each latch circuit includes a resetting control circuit, a setting control circuit, a data transmission circuit, and a latch transmission circuit. The resetting control circuit is coupled to a first data node and configured to receive a first supply voltage, so as to determine a potential of the first data node. The setting control circuit is coupled to a second data node and configured to receive the first supply voltage, so as to determine a potential of the second data node. The data transmission circuit is coupled to the first data node and the second data node and configured to receive a second supply voltage. The latch transmission circuit is coupled to the first data node, the second data node, and a sense node. The first supply voltage is higher than the second supply voltage.

The invention provides a data transmission circuit, a data receiving end, a data transmission method and a display device, belongs to the field of communication protocols, aims to improve the transmission efficiency of the data transmission circuit, is connected between a sending end and the receiving end, and comprises at least one pair of data lines configured to transmit electric signals corresponding to display data to be sent by the sending end; a pair of clock lines configured to provide a synchronous clock signal for an electrical signal transmitted on the data line; the first current flow direction sensor is connected between two data lines in the pair of data lines, is suitable for being connected with a receiving end, and is configured to provide a first current flow direction between the electric signals on the pair of data lines for the receiving end; and the second current flow direction sensor is connected between the at least one pair of data lines and one clock line in the pair of clock lines, is suitable for being connected with a receiving end, and is configured to provide a second current flow direction between the electric signals transmitted on the pair of data lines and one clock line for the receiving end.

The disclosed data transmission circuit and a memory include a sense amplifier circuit, a first sub-discharge path, a second sub-discharge path, and a discharge adjustment unit. The sense amplifier circuit generate amplified signals based on two terminals. The first sub-discharge path, in the read state, discharges at the first terminal to the discharge terminal based on the first data line signal; the second sub-discharge path, in reading state, discharges at the second terminal to the discharge terminal based on the discharge adjustment signa. The discharge adjustment unit is electrically connected to the second sub-discharge path and the control signal, but is not connected to the first sub-discharge path, and is used for generating the discharge adjustment signal based on the control signal, to adjust the discharge capacity of the second sub-discharge path. The present disclosure improves the anti-interference ability and data transmission efficiency of the data transmission circuit.

The invention discloses an anti-radiation data transmission circuit, device and system, the anti-radiation data transmission circuit comprises a crystal oscillator oscillation starting circuit and a data transmission link, and the crystal oscillator oscillation starting circuit and the data transmission link are structurally enhanced by adopting an annular gate reinforcement technology; the crystal oscillator oscillation starting circuit comprises an external signal branch and an external crystal oscillator branch which are mutually backed up; and the data transmission link is used for converting the basic frequency signal output by the external signal branch or the external crystal oscillator branch into high-speed serial data and sending the high-speed serial data to the off-chip receiving module. According to the application, firstly, a redundant data source, namely an external signal branch and an external crystal oscillator branch which are mutually backed up, is provided, so that the data transmission reliability is improved, and meanwhile, the data reinforcement based on the annular gate is carried out on the first receiving module and the data transmission link, so that the reliability of data transmission is improved. And a high-stability data transmission link is constructed in combination with an external crystal oscillator with anti-radiation capability, so that the anti-radiation capability of the whole data transmission circuit is improved.

The utility model provides a non-contact data transmission circuit for a CT (Computed Tomography) machine, which comprises an optical signal-to-electric signal circuit, a radio-frequency signal transmitting circuit, a radio-frequency signal receiving circuit and an electric signal-to-optical signal circuit, and the input end of the optical signal-to-electric signal circuit can receive optical signals output by an optical signal output module of the CT machine. The output end of the optical signal-to-electric signal circuit is connected with the input end of the radio frequency signal transmitting circuit, the output end of the radio frequency signal transmitting circuit is in wireless communication connection with the input end of the radio frequency signal receiving circuit, and the output end of the radio frequency signal receiving circuit is connected with the input end of the electric signal-to-optical signal circuit. And the output end of the electric signal-to-optical signal circuit can be connected with the input end of a computer optical signal receiving module. The CT machine has the advantages that high-speed data transmission of the CT machine can be achieved, and optical signals are not prone to external interference.

The utility model relates to the technical field of motorcycle instruments, and particularly discloses a multifunctional motorcycle instrument panel which comprises an instrument panel shell, a display screen is installed on the instrument panel shell, and a PCB electrically connected with the display screen is arranged in the instrument panel shell. The PCB comprises a main control circuit, a power supply step-down circuit, a remote control receiving circuit, an audio power amplifier circuit, a key control circuit and a data transmission circuit, and the power supply step-down circuit, the remote control receiving circuit, the audio power amplifier circuit, the key control circuit and the data transmission circuit are all electrically connected with the main control circuit. The remote control receiving circuit is matched with the master control circuit to receive audio signals, and the audio signals are output after being amplified by the audio power amplifier circuit, so that the functions of playing music, a radio and the like are realized, the functions are diversified, the practicability is high, and the use requirements of users can be met.

The application discloses a kind of in-furnace temperature measuring device, temperature measuring method and computer readable storage medium, in-furnace temperature measuring device includes tray, connecting structure, power supply structure and multiple test batteries, each test battery is provided with multiple temperature measuring probes;Cavity is used to place test battery;Connecting structure includes temperature measuring instrument, temperature measuring instrument is connected with tray, temperature measuring instrument includes wireless receiving end and temperature measuring channel connected with temperature measuring probe, wireless transmitting end is connected with external device, external device is provided with wireless receiving end, wireless receiving end is matched with wireless transmitting end to switch on data transmission circuit, and data transmission circuit is used to transmit the temperature information of test battery;Power supply structure is connected with tray, and power supply structure is electrically connected with temperature measuring instrument.The application is switched on data transmission circuit by temperature measuring probe, wireless transmitting end and wireless receiving end cooperation, realizes the cavity station in single body furnace to carry out furnace temperature temperature test, avoids the installation wiring difficulty caused by wiring mode transmission data and so on.

The invention relates to the field of semiconductors, provides a memory, and aims to reduce the power consumption of the memory on the premise of not increasing the area of the memory. The memory comprises a memory array, a data transmission circuit and a peripheral circuit, the data transmission circuit is arranged between the storage array and the peripheral circuit and is used for data transmission between the storage array and the peripheral circuit; the data transmission circuit comprises a first data path and a second data path in the data transmission direction. The power end of the first data path is electrically connected with the first transmission line, and the grounding end is electrically connected with the second transmission line; the power end of the second data path is electrically connected with the second transmission line, and the grounding end is electrically connected with the third transmission line; wherein the first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, the third transmission line is electrically connected with the common grounding end, and the voltage value of the first power supply voltage is larger than that of the second power supply voltage.

The application provides a data transmission circuit and method based on signal conversion, a chip and an electronic device, and belongs to the field of circuits.The data transmission circuit based on signal conversion comprises a first conversion module and a second conversion module.The first conversion module is used for receiving a parallel signal from a first clock domain and converting the parallel signal into a serial signal of a second clock domain, wherein the frequency of the first clock domain is less than the frequency of the second clock domain.The second conversion module is used for receiving the serial signal and converting the serial signal into the parallel signal.The scheme realizes the transmission of the parallel signal from the first conversion module to the second conversion module within a first clock cycle.By applying the data transmission circuit based on signal conversion to transmit signals between FPGAs, a large number of signals can be transmitted from one FPGA to another FPGA within a clock cycle, thereby reducing the difficulty of circuit design and timing convergence.

Provided are a data transmission circuit system and a data reception circuit system, which use an edge of a pulse signal. The data transmission circuit system modulates a digital signal by using time levels determined based on time differences between rising edges and falling edges of a clock pulse signal, and rising edges and falling edges of a data pulse signal. The data reception circuit system demodulates a digital signal by using time levels determined based on time differences between rising edges and falling edges of a recovered clock pulse signal, and rising edges and falling edges of a data pulse signal.

The application provides a UCIe standard protocol layer data transmission circuit, a related method and a chip. The circuit comprises: a slicing circuit configured to split data packets from a service port; a framing device configured to send a slice frame and slice description information associated with the slice frame to a framing device; the framing device is configured to fill the slice frame and the slice description information associated with each slice frame from each slicer into a flow control unit Flit, and send the Flit to a deframer; the deframer is configured to determine the slice frame belonging to the same service port from the Flit, and send the slice frame and the slice description information associated with the slice frame to the packet assembly circuit corresponding to the service port; the packet assembly circuit is configured to splice and output the data packets in the slice frame based on the slice description information. The existing UCIe standard protocol layer data transmission needs to introduce a large multiplexer, which causes a technical problem of inserting a snapshot and introducing additional delay.

A touch microcontroller unit including a touch data acquisition circuit to acquire touch data of a first area and a second area of a first panel. The touch microcontroller unit including an area division boundary calculation circuit to calculate a boundary in the first panel to divide the first area and the second area. The touch microcontroller unit including a touch coordinate calculation circuit to calculate touch coordinates of the first area based on the touch data of the first area. The touch microcontroller unit including a touch data transmission circuit to transmit the touch coordinates of the first area and the touch data of the second area to another touch microcontroller unit.

The utility model discloses an on-chain identity identification label device for bicycle traceability. The on-chain identity identification tag device comprises a main controller embedded in a bicycle body, a near field communication (NFC) chip, an anti-disassembly detection circuit, a data transmission circuit, a power management module, a sensor combination, a crystal oscillator, an analog-to-digital converter, a display screen and a two-dimensional code display layer, wherein the main controller is respectively connected with the NFC communication chip, the anti-tamper detection circuit, the data transmission circuit, the power management module, the sensor combination, the crystal oscillator, the analog-to-digital converter, the display screen and the two-dimensional code display layer, and the NFC communication chip is respectively connected with the anti-tamper detection circuit, the sensor combination, the crystal oscillator and the data transmission circuit. And the sensor combination is respectively connected with the data transmission circuit and the analog-to-digital converter. According to the utility model, the tamper-proof detection of the bicycle label is realized, and the integrated target of tamper-proof and hardware binding is realized on the physical structure.

A multi-core processor includes a plurality of processor cores and a data transfer circuit. The processor cores include a first processor core and a second processor core. The first processor core has a first buffer, and writes a first data into the first buffer. The second processor core has a second buffer. The data transfer circuit performs a polling operation upon the first buffer to check if the first buffer has data waiting to be transferred, and transfers the first data from the first buffer to the second buffer, wherein the first data is transferred inside the multi-core processor only.

A memory device and an operating method thereof are provided. The memory device includes: a latch configured to sense a voltage or current of a bit line coupled to a memory cell and store read data; a transmission circuit configured to output the read data stored in the latch via a page bus in response to a transmission signal; a cache latch configured to receive the read data via the page bus and temporarily store the read data; and a pump voltage output circuit coupled to the transmission circuit via a transmission line and configured to apply a second voltage greater than the first voltage after applying a first voltage to the transmission line for a set time.

Techniques are described for efficiently and reliably managing machine check exceptions. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions; a plurality of machine check architecture (MCA) banks coupled to the plurality of cores, each MCA bank comprising a plurality of MCA registers to store machine check data (MCD); MCD transmission circuitry to transmit a packet to an error monitoring server, the MCD transmission circuitry to generate a header of the packet using header information stored in one or more packet configuration registers and to generate a payload of the packet using at least a portion of the MCD stored in one or more of the MCA registers.

The present invention discloses a bite detection and analysis system integrating two-dimensional images of dental arches and an implementation method. The system includes: a flexible force sensor for detecting the magnitude of the biting force; a support frame for fixing the flexible force sensor and fixedly connected to one end of a transmission handle; a data transmission circuit is arranged inside the transmission handle to transmit the data of the flexible force sensor to a display terminal; a display terminal for displaying the biting force distribution according to the received data of the flexible force sensor; and an optical sensing device for acquiring two-dimensional images of dental arches. The bite detection and analysis system combined with the flexible force sensor, the support frame, the transmission handle, and the display terminal of the present invention can achieve the advantages of rapid extraction of the two-dimensional shape of the dental arch, good adaptability, high accuracy, and low cost, saving the time for medical staff to compare and process later and reducing the quantization error of the bite detection and analysis system.

To provide a semiconductor storage device that can improve bus utilization efficiency.SOLUTION: A semiconductor storage device includes a data holding part, a data transfer circuit, and a control part. The data holding part temporarily holds data read from a memory cell array. The data transfer circuit is provided between the data holding part and a pad part and transfers the data held in the data holding part to an input / output pad. The data transfer circuit is provided with a blocking part capable of blocking a current supply to the data transfer circuit. When a predetermined time has elapsed without data transfer to a memory controller after the data has been transferred to the data transfer circuit from the memory cell array via the data holding part, the control part blocks the current supply to the data transfer circuit by means of the blocking part. The predetermined time is changeable.SELECTED DRAWING: Figure 2

The utility model relates to the technical field of integrated circuits, in particular to an expansion circuit and a hub. The circuit is characterized in that when external USB equipment is inserted into a port circuit, a control circuit detects that a voltage jump signal appears in the port circuit through a first detection circuit, and the control circuit detects a port serial number of the port circuit inserted with the external USB equipment through a second detection circuit; and the control circuit controls the data transmission circuit according to the port serial number, so that the external USB equipment is in a data transmission state. According to the circuit, a computer can accurately identify which specific port of the concentrator is connected with external equipment, so that the equipment can be directly operated.

A data transmission circuit and method, a core, a multi-core chip, an electronic device, and a storage medium are disclosed. The data transmission circuit includes a receiving unit, a control unit, a lookup table unit, and a selection unit. The receiving unit receives original data packets from Fabric. The control unit determines whether the original data packet needs relaying based on an original control bit. In response to the need for relaying, the control unit activates a first input terminal of the selection unit, which then sends a new data packet to Fabric via the first input terminal. The new data packet includes the original data and a new header obtained by the lookup table unit based on the original index. This data transmission circuit effectively reduces power consumption during data transmission between multiple cores.

A data transmission circuit is improved to support a data transmission mode suitable for an interface or an application according to selection of an option. The data transmission circuit includes a pre-driver configured to output a first differential drive signal, a second differential drive signal, and a pre-emphasis control signal by using a first differential data signal, a second differential data signal, and an option signal; a main driver configured to output a first differential transmission signal and a second differential transmission signal by using the first differential drive signal and the second differential drive signal; and a pre-emphasis driver configured to perform pre-emphasis of different amplification degrees on the first differential transmission signal and the second differential transmission signal in a first mode and a second mode by the pre-emphasis control signal.