The embodiment of the invention provides a
system-on-
chip high-speed interface architecture, a working method of the
system-on-
chip high-speed interface architecture, a
chip and communication equipment, and relates to the technical field of SOC chip high-speed interface communication. According to the
system-on-chip high-speed interface architecture, a common
physical layer module is introduced to replace the mode that independent
physical layer modules are configured for a serial fast input and output protocol and a 10-
gigabit Ethernet protocol respectively in a traditional design, and the common
physical layer module can support physical layer
signal transmission of the two protocols at the same time; in combination with the flexible configuration of the working mode and the selective routing of the
data path by the control module, the sharing of physical layer resources is realized, thereby effectively reducing the occupation of the chip area, reducing the overall
power consumption, avoiding the increase of the development cost caused by the repeated configuration of the physical layer module, and improving the development efficiency. And the
resource utilization efficiency and the
system integration degree of the chip of the system-on-chip in the high-speed
interface design are improved.