311 results about "Transceiver chip" patented technology

An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

A transceiver system according to the present invention transmits data utilizing the baseband and one or more frequency separated transmission bands. A baseband transmitter is combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. A baseband receiver is combined with one or more receivers that receive data from the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands). A transceiver circuit or chip according to the present invention includes a transmitter and a receiver and communicates with a corresponding transceiver chip. In some embodiments, one baseband PAM transmitter is combined with one frequency separated QAM transmitter.

Multi-mode-multi-band direct conversion receiver with complex I and Q channel interference mitigation processing for cancellation of intermodulation products are described. In one embodiment, a method comprising over sampling of the entire receiver passband to acquire the IMP source signals that can generate IMPs within the SOI, using these signals to generate a coherent complex I-Q channel estimates of the interference and (after phase and amplitude adjustment) using these estimates to cancel the SOI inband IMPs in the I and Q channels independently and simultaneously in near real time, generating estimates of 2^nd and 3^rd order IMP products, adjusting the phase and amplitude of the estimates and using the estimates to cancel the SOI inband IMPs on the I ad Q channels independently and simultaneously in real time or very near real time, sampling of the transmitter feed thru signal and blocking signals and computing the cross modulation products estimate and adjusting the phase and amplitude and using the estimate to cancel the SOI inband cross modulation products energy in real time or near real time in the I and Q channels of the receiver, using the cross modulation cancellation to cancel of the effects of the on chip transmitter feed thru to support building a single transceiver chip with full duplex operation with cancellation being done independently and simultaneously on the I and Q channels of the receiver, and creation of an estimate of the DC offset in the receiver and adjusting the amplitude of the DC offset in a near real time closed loop fashion to cancel the DC offset in the I and Q channels independently and simultaneously and adjusting the rate of update to match system parameters.

Methods, systems, and devices are described for transceiver architecture for millimeter wave wireless communications. A device may include two transceiver chip modules configured to communicate in different frequency ranges. The first transceiver chip module may include a baseband sub-module, a first radio frequency front end (RFFE) component and associated antenna array. The second transceiver chip module may include a second RFFE component and associated antenna array. The second transceiver chip module may be separate from the first transceiver chip module. The second transceiver chip module may be electrically coupled to the baseband sub-module of the first transceiver chip module.

A method and apparatus for 2× oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter environments and can be implemented with small hardware overhead. A transceiver that embodies the invention can be implemented as a CMOS integrated circuit using a 0.18 μm CMOS process, with the transceiver chip being capable of recovering data having a data rate of up to 11.5 Gbps from a signal received over a serial link, while consuming no more than 540 mW from 1.8V supply, and with a bit error rate of less than 10⁻¹².

An anti-metal radio frequency identification (RFID) tag and a manufacturing method thereof are described. The anti-metal RFID tag includes a substrate having a first surface and a second surface on an opposite side thereof; a planar integral antenna formed on the first surface of the substrate; a RFID transceiver chip (i.e., RFID chip) disposed on the surface of the substrate and coupled to a signal feed point of the planar integral antenna. The flexible planar integral antenna and substrate are folded and then fixed by a fixing mechanism to form an anti-metal RFID tag with a feed-in structure, a RFID transceiver chip, and a radiator on one side, and a ground plane on the opposite side. A spacer is further sandwiched in the center of the folded structure, which is helpful for improving the antenna gain of the anti-metal RFID tag.

An RF front-end architecture is operated in either a transmitting or a receiving mode. The RF front-end architecture comprises an antenna, an impedance match network, a balun and a transceiver chip. The transceiver chip comprises first and second transmit/receive (TR) switches, a transmitter, and a receiver. Because two TR switches are integrated into the chip, the printed circuit board area, BOM cost and pin count of the transceiver chip can be greatly reduced.

A method and system are disclosed for providing standalone built-in self-testing of a transceiver chip. The transceiver chip includes packet generators for generating test packets and packet checkers for comparing received packets with expected packets. The transceiver chip may be configured for testing through at least two wraparound test paths—a first test path that includes an elastic FIFO of a transmit path of the transceiver chip, and a second test path that includes an elastic FIFO of a receive path of the transceiver chip. During testing, the test packets are generated by packet generators within the transceiver chip and routed through the at least two wraparound test paths to packet checkers within the same transceiver chip. The packet checkers compare the returned packets to the expected packets. If the returned packets are inconsistent with the expected packets, the transceiver chip is defective.

Methods and systems for processing data are disclosed herein and may include compressing audio information on-chip within a Bluetooth® transceiver chip utilizing an audio codec implemented within the Bluetooth® transceiver chip. The audio codec may be a low complexity sub-band codec (SBC). An audio stream with the audio information may be generated outside the Bluetooth® transceiver chip. The audio stream may be generated via an audio/video distribution transport protocol (AVDTP) external to the Bluetooth® transceiver chip. A data channel may be established by the Bluetooth® transceiver chip between a Bluetooth® enabled device and a peer Bluetooth® device, for communicating the established audio stream to the Bluetooth® transceiver chip for compression. The data channel may be established utilizing a logical link control and adaptation protocol (L2CAP) and/or an advanced audio distribution profile (A2DP).

The invention discloses a smart factory-based multi-function data acquisition device, acquisition system and method. The acquisition device comprises a microprocessor as well as a power supply module, a 485 transceiver chip, a 232 transceiver chip, an IO signal conversion circuit and two Ethernet protocol stack chips which are connected with the microprocessor, wherein the 485 transceiver chip and the 232 transceiver chip are respectively provided with an RS-485 Interface and an RS-232 interface which are used for connecting external devices and acquiring device data, the Ethernet protocol stack chips are provided with Ethernet interfaces and are used for connecting upper computers or other acquisition devices and transmitting data, and the IO signal conversion circuit is provided with an IO port and is used for connecting external devices, acquiring signals or controlling the devices. The data acquisition device can be configured to a master station mode or a slave station mode, and is flexible in interfacing, and therefore, the data acquisition device can read data of field devices and scattered acquisition points more economically, conveniently and efficiently and provide complete and accurate bottom data for the establishment of a smart factory.

The invention discloses a PHS mobile phone which comprises an antenna, a front end filter, an antenna switch, a radio frequency power amplifier, a radio frequency transceiver chip, a baseband chip, a memory and a peripheral device. The antenna, the front end filter, the antenna switch, the radio frequency power amplifier, the radio frequency transceiver chip and the baseband chip are connected in turn, and the baseband chip is further connected with the memory and the peripheral device respectively. The invention further discloses a transmission power control method of the PHS mobile phone. The PHS mobile phone can adjust the transmission power of the PHS mobile phone at all times according to the strength range of received signals. The transmission power of the PHS mobile phone is increased in the weak signal area, and the transmission power of the PHS mobile phone is reduced in the stronger signal area.

In current applications, when a short distance wireless transceiver chip transmits and receives data, transmitting power and receiving power are fixed, usually in order to achieve the purpose of signal communication, the data are transmitted and received by utilization of maximum power/maximum gain, in actual applications, under most conditions, the data are not needed to be transmitted and received by utilization of the maximum power/maximum gain, and extremely large waste of power consumption is caused. The invention provides a method dynamically controlling the transmitting power and the receiving power of the transceiver chip, communication equipment and a communication system based on an RSSI, the transmitting power and the receiving power are further lowered according to the actual applications, the power consumption is reduced, and the service life of a battery is prolonged.

The invention provides a 400 Gbps hot-plug high-speed optical transceiver module which is suitable for the optical communication technical field. The 400 Gbps hot-plug high-speed optical transceiver module comprises an optical interface unit, a photoelectric transceiver unit and an electrical interface unit; the photoelectric transceiver unit is used for achieving the functions of photoelectric conversion and high-speed electrical signal processing through a photoelectric transceiver chip; the internal working process of the photoelectric transceiver chip comprises receiving an electrical signal input through the electrical interface unit by a transmitting terminal data clock recovery circuit, loading the electrical signal to a laser after the pretreatment through a driving circuit, converting the high-speed electrical signal into a high-speed optical signal through the laser, reusing the high-speed optical signal through a wavelength division multiplexer to be output, reusing the received optical signal into a 16-channel optical signal through a wavelength division demultiplexer to be transmitted to an optical detector and transmitting the 16-channel optical signal to a trans-impedance amplifier and a receiving terminal data clock recovery circuit after photoelectric conversion to be processed. According to the 400 Gbps hot-plug high-speed optical transceiver module, the factors such as the cost, the transmission loss, the chromatic dispersion and the size are considered to select different optical transceiver modules and accordingly the long-distance single-mode optical fiber transmission or the short-distance multimode transmission is implemented.

The invention provides a distributed communication-in-motion light shaped antenna which is composed of a plurality of distributed front ends (9), a distributed optical fiber signal network (6), a distributed low-frequency signal network (7) and a distributed grating sensor network (8). Each of the distributed front ends comprises a distributed antenna sub-array (1), an electro-optical/photoelectric conversion chip (3), a sub-array wave beam control system (4) and a grating sensor (5), which are electrically connected around a silicon-based integrated transceiver chip (2). Under command control of a centralized processing terminal (10), each distributed front end (9) can implement beam scanning and satellite signal alignment; and then the plurality of distributed front ends (9) implement beam forming and real-time satellite communication under command control of the centralized processing terminal (10). The technical problem that the existing communication-in-motion antenna is designed in an integrated mode in an aperture, is large in size and heavy, and is hard to match a flexible wing structure in stiffness is solved.

A millimeter wave (MMW) transceiver module includes a microwave monolithic integrated circuit (MMIC) transceiver chip set that is surface mounted on a circuit board. The MMIC transceiver chip set includes a receiver MMIC chip package, a transmitter MMIC chip package, and a local oscillator (LO) multiplier MMIC chip package. Each MMIC chip package includes a base and a multilayer substrate board formed from layers of low temperature transfer tape. The multilayer substrate board has at least three layers and carries RF signals, DC signals, grounding and embedded passive components, including resistors and capacitors. At least one MMIC chip is received on the multilayer substrate board.