42results about "Synchronisation transmitters" patented technology

A dual-mode transmitter for a low-power double-data rate (LPDDR) interface can be operated in one of a non-return to zero (NRZ) mode and a pulse amplitude modulation (PAM)-4 mode. The dual-mode transmitter includes: a pseudorandom binary sequence (PRBS) generator configured to generate a transmission signal to be transmitted to a dual-mode receiver; at least one serializer configured to serialize the transmission signal; a single-ended to differential (S2D) configured to convert the serialized transmission signal in a form of a single-ended signal into a differential signal; a ZQ calibration configured to generate a result code for matching an impedance value at an output terminal of the dual-mode transmitter with a terminating resistance value of the dual-mode receiver; and a pre-driver configured to combine the differential signal obtained by the converting and the result code.

A method of generating a synchronization signal comprises synchronizing, by a first wireless user device (410, 430, 440, 450, 460, 470, 900, 950), a timing of a synchronization signal received from a synchronization source, wherein the timing of the synchronization signal is associated with a synchronization timing of a Global Navigational Satellite System, GNSS, determining a subframe to transmit a primary sidelink synchronization signal, PSSS, and a secondary sidelink synchronization signal, SSSS, mapping the SSSS to two consecutive single frequency-frequency division multiple access, SC-FDMA, symbols in the determined subframe, and transmitting, from the first wireless user device to a second wireless user device, the PSSS and the SSSS in the determined subframe. The mapping the SSSS comprises generating a first length-31 sequence based on ml, generating a second length-31 sequence based on m0, where ml is greater than m0, and mapping, based on a first mapping scheme of two mapping schemes, the first length-31 sequence and the second length-31 sequence to 62 consecutive subcarriers in the two consecutive SC-FDMA symbols in the determined subframe, wherein a portion of the first length-31 sequence is mapped to a subcarrier having a lowest index among the 62 consecutive subcarriers and a portion of the second length-31 sequence is mapped to a subcarrier having a highest index among the 62 consecutive subcarriers.

The present invention provides an effective hardware architecture for a combined aggregation and distribution unit (CCDU) ​​ORAN-compliant clock synchronizer module for 5G foundation applications required to handle L1, L2, and L3 schedules of the network. The CCDU design can achieve CU and DU functionality in a single unit and can operate over a wide temperature range. The single board approach of the CCDU makes the CCDU more reliable and less costly. The CCDU can support different types of synchronization and can provide site alarms over dry contacts for accommodating external alarm devices.

A communication system uses a differential edge modulation scheme having one of four or more values and a clock pulse is also encoded in each unit interval. A four-valued encoding may be as follows: prior to each unit interval, two signals are both at the same value; at the start of the unit interval, a first one of the signals is transitioned to indicate a first bit of the symbol; after a selected one of two delay periods that are less than the unit interval, the other signal is transitioned to indicate a second bit of the symbol; after this transition, both signals are again at the same value. The transitioning, at the start of the unit interval, provides an edge that may be extracted and used a timing reference.

Systems, methods, and circuits for performing bidirectional communication using an edge time in a signal are provided. In one example, a method involves receiving a common signal on a signal line between one device and another. The common signal comprises a series of signal periods, and each signal period includes a first edge of a first type and a second edge of a second type, different from the first type. In each signal period of the series of signal periods, information to be communicated by the other device is determined at least based on the determined time of the first edge, and a time for a subsequent second edge with respect to the signal period is determined based on information to be communicated to the other device.The subsequent second edge is generated at the selected time in a subsequent signal period of the series of signal periods.

A channel between quantum controller modules (e.g., pulse processors) is operable to communicate high speed data required for processing qubit states that may be distributed across a quantum computer. The latency of the communication channel is deterministic and controllable according to a system clock domain.

Embodiments of this disclosure relate to communication using edge timing in signals. Systems, methods, and circuits are provided to perform bidirectional communication using edge timing. In an example, one method includes receiving a first signal on a first signal line, the first signal having a first timing edge and a first data edge. The first timing edge and the first data edge are of different types. The first data edge is an edge immediately adjacent to the first timing edge and occurs after a first elapsed time following the first timing edge. The method includes sampling the first signal for a predetermined sampling time after the first timing edge to determine a first data value. A second data value is determined, and a second signal having a second timing edge and a second data edge is generated. A second elapsed time between the second timing edge and the second data edge encodes the second data value. The second signal is transmitted on the second signal line.

[Problem] To provide a communication device and a communication system that perform serial communication at low power and at high speed. [Solution] The communication device comprises: a state-switching control unit for controlling switching between a first state that establishes synchronization for performing communication with a communication partner device, a second state that initiates communication after synchronization is established in the first state, a third state that causes communication to be intermittently stopped without losing the establishment of synchronization, and a fourth state that reestablishes synchronization with the communication partner device when communication is resumed after being stopped for a longer period than in the third state; a first communication control unit for repeating, on a first cycle, the operation of continuously transmitting a first signal within a first signal interval to the communication partner device when in the fourth state; a second communication control unit which, when a second signal outputted from the communication partner device in response to the first signal is received, transmits a third signal that is synchronized to the second signal to the communication partner device. The switching control unit causes transition from the fourth state to the first state when the second communication control unit transmits the third signal.

A network interface device includes packet processing circuity to capture a network packet transmitted by a software application running on a computing device and capture, at time of transmission of the network packet, a value of a physical clock as a receive timestamp for subscriber entities of the computing device. The circuitry associates the receive timestamp with a first packet copy of the network packet and inserts the first packet copy to a first receive pipeline of a first subscriber entity. The circuitry associates the receive timestamp with a second packet copy of the network packet and inserts the second packet copy to a second receive pipeline of a second subscriber entity.

The application provides a serial transceiver-based data transmission method, a transceiver, a medium and equipment, and the method comprises the following steps: a serial transceiver switches clock frequency in the process of transmitting frame data, sends clock frequency switching information to a sending end parallel-serial conversion unit, and repeatedly writes current frame data into a sending data buffer; the sending end parallel-serial conversion unit reads parallel valid data of a preset bit number in the current frame data, counts the read bit number through a counter, and after receiving the clock frequency switching information, judges whether the count value is equal to the preset bit number value; if yes, it is determined that the parallel valid data is serialized, and serial data is obtained; the receiving end serial-parallel conversion unit converts the serial data into parallel data, and after detecting a frame header in the parallel data, it is determined that the frame header is in the aligned frame data, and the frame data is written into a receiving data buffer. The application realizes switching of data transmission rate of the serial transceiver in the data transmission process.

The invention provides a synchronization method, a synchronization device, and a transceiver device for multi-channel data transmission. The synchronization method transmits test data to N receiving devices, obtains a transmission cycle and N delayed playback timestamps based on the information fed back by the receiving devices, the data packet preparation time, a first time, and a predetermined error tolerance time; transmits audio data packets to the N receiving devices, obtains an existing data playback duration and a time difference based on the acknowledgment packets fed back by the receiving devices; adjusts the predetermined error tolerance time to a target error tolerance time according to the comparison result between the time difference and a predetermined time difference threshold. This achieves real-time and timely adjustment of the delayed playback time of audio data packets according to the actual situation of data transmission, thereby achieving the purpose of audio synchronization in multi-channel wireless transmission.

The invention discloses a communication system, a communication method, a host computer, a slave computer and a device with master-slave communication, the communication system comprises the host computer and at least one slave computer, and the host computer is in communication connection with the at least one slave computer for data interaction; the host sends host data, the data frame format of the host data comprises a frame type selection bit, the value of the frame type selection bit represents a target state machine of a target slave selected by the host, and the target slave is a slave which performs data interaction with the host in the at least one slave. According to the communication system and method, the data processing amount of the target slave can be reduced, and the data processing efficiency of the slave is improved.

Various example embodiments relate to partial data transmission. A transmitter may receive at least one dataset for transmission. The dataset may be one of a plurality of datasets known to the transmitter and a receiver or to be signaled to the receiver. The transmitter may determine a first portion of the dataset. The size of the first portion may be determined based on a battery level indicator, a latency level associated with the dataset, a radio condition, or a network load. The receiver may recognize the dataset based on the first portion and / or at least one second portion transmitted by the transmitter. Apparatuses, methods, and computer programs are disclosed.

A data transmitter with a phase detector, average duty cycle sensor and phase sampler to optimize a clock / data paths. Phase and duty cycle information are provided to a digital control to adjust a timing in the data path and clock path, respectively. The phase detector reads a skew between the data and negative and positive phase clock signals inside a driver. An optimal pulse width delta is determined by the target duty cycle sensor. Using a measured averaged duty cycle sensor, the digital control calculates the duty cycle error to the target value that is needed inside the driver. The phase sampler has a multiplexer which routes the clock signals to phase sensors which determine a phase error based on, e.g., a rising edge-to-rising edge comparison and a falling edge-to-falling edge comparison. In addition, it includes a duty cycle sensor for each clock phase.

The application provides a signal sampling time determination method, device and terminal equipment, and relates to the technical field of communication. The signal sampling time determination method comprises the following steps: obtaining a signal estimation error in a first sampling interval; the first sampling interval is an interval between a first signal sampling time and a second signal sampling time; obtaining a signal sampling error threshold of a second sampling interval according to the signal estimation error in the first sampling interval and a time length of the first sampling interval; determining a third signal sampling time according to the signal sampling error threshold of the second sampling interval and a first sampling signal sent at the second signal sampling time; the second sampling interval is an interval between the second signal sampling time and the third signal sampling time; and the second signal sampling time is located before the third signal sampling time. The signal sampling time obtained in the application is used for sending a sampling signal, which can reduce a signal estimation error obtained by terminal signal estimation and increase the accuracy of estimated signal state information.

A system comprising transmission circuitry to communicate first data to receiver circuitry over a serial communication link during an active state of the serial communication link; and power adjustment circuitry to adjust a power level of the transmission circuitry responsive to a request based on at least one margin measurement performed by the receiver circuitry on the first data, wherein the transmission circuitry is to communicate second data using the adjusted power level over the serial communication link.

Technologies for a jitter injection generator and a spectrum hardware engine for measuring and assessing phase noise and jitter transfer function are described. One communication device includes a timing and synchronization circuit that generates a signal with time-domain data, and a spectrum hardware engine. The spectrum hardware engine converts this data into frequency-domain data. It has registers storing past outputs, multipliers for computing products using these values and a pre-computed coefficient, and a summation block for combining the current input with these products to get the current output. This output is sent to the computing device to estimate phase noise.

A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes performing a link equalization operation, checking a transmission mode of the interface device, and determining a transmission parameter of the interface device based on a status of the first elastic buffer or a status of a second elastic buffer included in another interface device communicating with the interface device when the transmission mode is a transmission parameter adjustment mode.

In one embodiment, a method comprises identifying at a first powered device in communication with power sourcing equipment, a second powered device in communication with the first powered device, wherein the first powered device is receiving high voltage pulse power from the power sourcing equipment, notifying the power sourcing equipment of the second powered device at the first powered device, and performing a low voltage power initialization at the first powered device with the second powered device before passing the high voltage pulse power to the second powered device. The first powered device comprises a local isolation switch for a first low voltage pulse power initialization with the power sourcing equipment at start-up of the first powered device and for receiving the high voltage pulse power from the power sourcing equipment and an output isolation switch for said low voltage power initialization with the second powered device and for passing the high voltage pulse power to the second powered device.

The invention relates to the technical field of industrial automation data aggregation and remote transmission, in particular to a temperature transmitter multi-node data aggregation and remote transmission system. Comprises: a beat clock generation unit for periodically broadcasting a beat clock signal not containing address information to announce the start of a data encoding period; the at least one asynchronous pulse coding unit is used for responding to the beat clock signal, autonomously coding node identity information and temperature data of the asynchronous pulse coding unit into a single asynchronous time sequence coding pulse relative to the beat clock signal, and sending the single asynchronous time sequence coding pulse to the shared channel; and the asynchronous time sequence mode identification unit is used for passively monitoring and receiving the asynchronous time sequence coded pulse on the shared channel by taking the beat clock signal as a reference. According to the method, the contradiction that a large amount of computing resources are consumed ineffectively for a long time in order to deal with small-probability emergencies is solved, and the rigid restriction relationship between the risk discrimination precision and the system response timeliness is broken through.

This invention relates to the field of industrial automation data aggregation and remote transmission technology, specifically a multi-node data aggregation and remote transmission system for temperature transmitters. It includes: a clock generation unit for periodically broadcasting a clock signal without address information to announce the start of a data encoding cycle; at least one asynchronous pulse encoding unit for responding to the clock signal, autonomously encoding its node identity information and temperature data into a single asynchronous time-series encoded pulse relative to the clock signal, and sending it to a shared channel; and an asynchronous time-series pattern recognition unit for passively listening to and receiving asynchronous time-series encoded pulses on the shared channel, using the clock signal as a reference. This invention resolves the contradiction of long-term, ineffective consumption of large amounts of computing resources to cope with low-probability sudden events, and breaks the rigid constraint between risk identification accuracy and system response timeliness.

The embodiment of the invention discloses a data processing device and a data driving device, and the data processing device comprises a first data mapping part which converts original data into a plurality of data packets; and an encoder that inverts a portion of bits of the plurality of packets; the encoder includes: a data comparison section that compares a most significant bit (MSB) of a first packet and a least significant bit (LSB) of a second packet adjacent to each other among a plurality of packets; a code conversion unit that, when the most significant bit of the first packet and the least significant bit of the second packet are the same, inverts the least significant bit of the second packet; and a bit generation unit that generates an instruction packet in which conversion information for the least significant bit of the second packet is stored.

A method of encoding input data includes dividing the input data into a plurality of data packets, an input packet of the plurality of data packets including a plurality of digits in a first base system, base-converting the input packet from the first base system to generate a base-converted packet including a plurality of converted digits in a second base system, the second base system having a base value lower than that of the first base system, and incrementing the converted digits to generate a coded packet for transmission through a communication channel.

A network node including a physical layer transceiver (106) and a physical layer transceiver. The transceiver includes a media independent interface (200), a converter circuit block (210) including circuit elements (214) configured to convert digital signals to analog signals for transmission over a network communication medium and to convert analog signals received over the medium to digital signals, and one or more processing blocks (202A, 202B, 202C) configured to process digital data communicated between the media independent interface and the converter circuit block in accordance with a network protocol. A management and control circuit element (220) including power management circuit elements and reset circuit elements is provided. The transceiver further includes at least one single event effect (SEE) monitor (240), such as an environmental monitor (242), a configuration register monitor (244), a state machine monitor (246), or a phase locked loop (PEL) lock monitor (250) configured to detect and respond to SEE events in the transceiver.

The embodiment of the invention discloses a data synchronization method, device and system. In a scene of synchronizing data streams of a physical layer, the synchronization process of the data streams can be timed. Furthermore, whether the data stream with the time length meeting the timeout condition exists in the synchronization process is judged, which is equivalent to whether the situation that the synchronization time is too long exists. If the condition that the synchronization time is too long exists, it is indicated that a system fault or link deterioration may occur, then corresponding timeout processing, such as error reporting and system resetting, needs to be carried out, so that the system fault or link deterioration can be dealt with in time, and the data transmission efficiency is optimized.

Systems and techniques are provided for an autonomous vehicle (AV) to select a mobile network. An example method can include establishing a connection between the AV and a mobile device associated with a passenger of the AV; identifying, using the connection, a first mobile network associated with the mobile device; determining that the first mobile network associated with the mobile device is different than a second mobile network associated with the AV; determining, based on a first network indicator associated with the first mobile network and a second network indicator associated with the second mobile network, that the first mobile network is preferable to the second mobile network; and initiating a mobile connection between the AV and the first mobile network.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

A signal transmitting method, an electronic device, and a communication system are provided. The signal transmitting method comprises: transmitting, by a transmitting terminal, a DQ redundancy code and a DQS preamble code to a receiving terminal during a preamble period, the DQ redundancy code is configured with a specific pattern such that jitter of a DQ signal tracks jitter of a DQS signal, and when the DQ redundancy code has the specific pattern, the lowest n bits of a pattern of the DQ redundancy code match the lowest n bits of a pattern of the DQS preamble code, where n is an integer greater than or equal to two; transmitting, by the transmitting terminal, the DQ signal and the DQS signal to the receiving terminal during a data transmission period. The signal transmitting method of the present disclosure helps to reduce timing loss.

In one embodiment, a method includes receiving low voltage pulse power from power sourcing equipment at a powered device, synchronizing the powered device with a waveform of the low voltage pulse power received from the power sourcing equipment, and operating the powered device with high voltage pulse power received from the power sourcing equipment.