196results about "Synchronisation transmitters" patented technology

The present invention provides an efficient hardware architecture for an ORAN compliant clock synchronizer module of a combined centralized unit and a distributed unit (CCDU) for a 5G basement application required for processing L1, L2 and L3 scheduling of the network. The CCDU design may provide the functionality of a CU and a DU with single unit and can operate over wide temperature range. A single board approach of the CCDU make the CCDU more reliable and less costly. The CCDU can support different kinds of synchronization and can provide site alarms over dry contacts to equip with external alarm device.

The invention provides a method and device for data signal transmission in network equipment, and the method comprises the steps: generating a data signal, the data signal comprises a delimiter and data, the delimiter comprises at least one first level pair, each first level pair comprises a low level and a high level, and each first level pair comprises at least one second level; the delimiter is used for identifying the starting position of the data, and the delimiter starts at a high level and ends at a low level; or, the delimiter starts at a low level and ends at a high level; and sending the data signal. According to the data signal transmission method provided by the embodiment of the invention, the accuracy of envelope detection output waveform timing can be improved, and the precision of the equipment for calibrating the own clock is further improved.

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

A device according to the present disclosure includes: a PLL configured to modulate and output a frequency of a clock used to synchronize communication data in accordance with a regulation signal applied thereto, and a controller configured to generate the regulation signal according to a modulation waveform which is a successive form of a plurality of modulation wave units determined by a set modulation profiled, and apply the regulation signal to the PLL. The modulation wave unit is a signal whose sum of signal values during its time length becomes zero for the first time, and at least two successive modulation wave units among the plurality of modulation wave units differ from each other in at least one of the time length and the form of the signal.

Ultra-Wideband (UWB) technology exploits modulated coded impulses over a wide frequency spectrum with very low power over a short distance for digital data transmission. Today's leading edge modulated sinusoidal wave wireless communication standards and systems achieve power efficiencies of 50 nJ / bit employing narrowband signaling schemes and traditional RF transceiver architectures. However, such designs severely limit the achievable energy efficiency, especially at lower data rates such as below 1 Mbps. Further, it is important that peak power consumption is supportable by common battery or energy harvesting technologies and long term power consumption neither leads to limited battery lifetimes or an inability for alternate energy sources to sustain them. Accordingly, it would be beneficial for next generation applications to exploit inventive transceiver structures and communication schemes in order to achieve the sub nJ per bit energy efficiencies required by next generation applications.

Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

A data transmission circuit including: an encoder configured to output a transition signal that indicates a transition state of an input data signal; a first serializer that receives the transition signal; an auxiliary driver configured to receive an output of the first serializer and drive an output node; a second serializer that receives the input data signal; and a main driver configured to receive an output of the second serializer and drive the output node.

The invention discloses a distributed phased array system and electronic equipment, and relates to the technical field of signal processing. Active transmit-receive units which are in one-to-one connection with the antenna units; a frequency source connected with each active transmit-receive unit and used for controlling frequency conversion synchronization in each active transmit-receive unit and performing synchronous calibration on a clock of each active transmit-receive unit; and the signal processing unit is connected with each active transceiving unit and is used for synchronizing the signal processing of each active transceiving unit based on the synchronously calibrated clock. By ensuring frequency conversion synchronization, clock synchronization and signal processing synchronization among the active transceiving units, the synchronism of transmission signals in the active transceiving units can be ensured, namely, the synchronism of multi-path signal input and output can be improved, and the synchronization performance among multi-path signal transceiving channels is improved.

A system includes a plurality of line cards and a timing card. A clock generation circuit on the timing card generates a clock signal which is pulse width modulated according to information to be transmitted. A clock line supplies the pulse width modulated clock signal to the line cards. The timing card sends a first control word to the plurality of line cards over the clock line after sending a beacon. The first control word includes a size field specifying a first length of first data following the first control word. The timing card sends time of day information over the clock line to the line cards following the first control word. The time of day information may be encrypted. A second control word follows the time of day information. One or more additional control words can follow the second control word before the next beacon.

The invention belongs to the technical field of multi-machine communication, and particularly relates to a multi-machine communication device and method for a 2.4 G wireless gamepad. Comprising a handle end; comprising a first handle and a second handle. The USB end is used for transmitting and receiving wireless data, performing wireless data interaction with the handle end and transmitting key value data to the PC; the private protocol is used for wireless data interaction; the time sequence synchronization module is used for synchronizing the receiving and transmitting time sequences of the USB end and the handle end; the self ID module is used for data interaction identification, and each USB end and each handle end respectively and independently have a unique ID; the mapping module is used for realizing mapping of a channel and an access address according to the ID module of the USB end; wherein the mapping of the channels is that the channels are mapped to 2402MHz-2530MHz according to the ID (Identity) of a USB (Universal Serial Bus) end in a user-defined manner, the interval between every two adjacent values is 1MHz, and the number of the channels is 129; the device has the advantages that the cost is low, the anti-interference performance is high, and the requirement that multiple sets of equipment work independently in the same space without interfering with one another can be met.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

The circuits and methods described herein provide a technical solution for technical issues for USB links. To reduce or eliminate the effects associated with the entry of a USB link into a low power mode, an initial link acquisition may be performed while disabling spread spectrum clock (SSC) modulation. After initial link acquisition, SSC modulation may be dynamically enabled at a later stage. This delayed activation of the retimer provides improved performance compared to a solution in which SSC modulation is continually activated, including reducing the complexity of the timing training process and enabling faster USB link re-establishment. This reduced link acquisition period may enable the system to enter the power saving mode more frequently and may reduce the latency involved in exiting the power saving mode. This may maintain or improve the overall USB transmission speed, and may reduce USB-related power consumption for USB-connected devices.

An apparatus for communication between a sending application and a receiving application of a receiving apparatus includes a processor that is configured to establish a stream for transmitting data between the sending application and the receiving application; receive a first request from the sending application to transmit metadata to the receiving application; receive a second request from the sending application to transmit application data to the receiving application; responsive to a determination that a frame that includes the application data and the metadata has a size that is smaller than or equal to a maximum frame size, construct the frame to include the application data and the metadata; and transmit the frame in a packet to the receiving apparatus.

The embodiments of the present application provide a method, device and system for sending precision information. The method includes: a first network element switches from a tracking state to a holding state; the first network element sends status information to a second network element, and the status information includes the precision information of the first network element in the holding state. Through the above method, the second network element can obtain the status information of the first network element in the holding state, and perform clock synchronization with the first network element or with the second network element according to the status information, ultimately achieving more accurate clock synchronization and further improving the performance of the clock synchronization system.

A device according to the present disclosure includes: a PLL configured to modulate and output a frequency of a clock used to synchronize communication data in accordance with a regulation signal applied thereto, and a controller configured to generate the regulation signal according to a modulation waveform which is a successive form of a plurality of modulation wave units determined by a set modulation profiled, and apply the regulation signal to the PLL. The modulation wave unit is a signal whose sum of signal values during its time length becomes zero for the first time, and at least two successive modulation wave units among the plurality of modulation wave units differ from each other in at least one of the time length and the form of the signal.

The embodiment of the invention discloses a data synchronization method, device and system. In a scene of synchronizing data streams of a physical layer, the synchronization process of the data streams can be timed. Furthermore, whether the data stream with the time length meeting the timeout condition exists in the synchronization process is judged, which is equivalent to whether the situation that the synchronization time is too long exists. If the condition that the synchronization time is too long exists, it is indicated that a system fault or link deterioration may occur, then corresponding timeout processing, such as error reporting and system resetting, needs to be carried out, so that the system fault or link deterioration can be dealt with in time, and the data transmission efficiency is optimized.

Communication with state-switching control is disclosed. In one example, a communication device includes a state-switching control circuit that controls switching between a first state in which synchronization for communicating with a partner device is established, a second state in which the communication is started after establishing the synchronization, a third state in which the communication is intermittently stopped, and a fourth state in which synchronization is reestablished when restarting the communication. A first communication control circuit repeats an operation of continuously transmitting a first signal to the partner device in the fourth state, and a second communication control circuit transmits, upon receiving a second signal, a third signal synchronized with the second signal to the partner device, in which the state-switching control circuit switches, where the second communication control circuit transmits the third signal, a state from the fourth state to the first state.

A dual-mode transmitter for a low-power double-data rate (LPDDR) interface can be operated in one of a non-return to zero (NRZ) mode and a pulse amplitude modulation (PAM)-4 mode. The dual-mode transmitter includes: a pseudorandom binary sequence (PRBS) generator configured to generate a transmission signal to be transmitted to a dual-mode receiver; at least one serializer configured to serialize the transmission signal; a single-ended to differential (S2D) configured to convert the serialized transmission signal in a form of a single-ended signal into a differential signal; a ZQ calibration configured to generate a result code for matching an impedance value at an output terminal of the dual-mode transmitter with a terminating resistance value of the dual-mode receiver; and a pre-driver configured to combine the differential signal obtained by the converting and the result code.

The present invention provides an efficient hardware architecture for an ORAN compliant clock synchronizer module of a combined centralized unit and a distributed unit (CCDU) for a 5G basement application required for processing L1, L2 and L3 scheduling of the network. The CCDU design may provide the functionality of a CU and a DU with single unit and can operate over wide temperature range. A single board approach of the CCDU make the CCDU more reliable and less costly. The CCDU can support different kinds of synchronization and can provide site alarms over dry contacts to equip with external alarm device.

A method of generating a synchronization signal comprises synchronizing, by a first wireless user device (410, 430, 440, 450, 460, 470, 900, 950), a timing of a synchronization signal received from a synchronization source, wherein the timing of the synchronization signal is associated with a synchronization timing of a Global Navigational Satellite System, GNSS, determining a subframe to transmit a primary sidelink synchronization signal, PSSS, and a secondary sidelink synchronization signal, SSSS, mapping the SSSS to two consecutive single frequency-frequency division multiple access, SC-FDMA, symbols in the determined subframe, and transmitting, from the first wireless user device to a second wireless user device, the PSSS and the SSSS in the determined subframe. The mapping the SSSS comprises generating a first length-31 sequence based on ml, generating a second length-31 sequence based on m0, where ml is greater than m0, and mapping, based on a first mapping scheme of two mapping schemes, the first length-31 sequence and the second length-31 sequence to 62 consecutive subcarriers in the two consecutive SC-FDMA symbols in the determined subframe, wherein a portion of the first length-31 sequence is mapped to a subcarrier having a lowest index among the 62 consecutive subcarriers and a portion of the second length-31 sequence is mapped to a subcarrier having a highest index among the 62 consecutive subcarriers.

Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

Frequency error tracking and lane monitoring techniques for multi-lane optical transceivers are provided. In one aspect, a method includes capturing phase and frequency information recovered by clock-and-data recovery circuits from data traveling along a plurality of lanes of an optical transceiver, with one of the lanes being a master lane; determining a frequency error based on the phase and frequency information of the master lane; outputting, by a tunable oscillator, a reference clock based on the frequency error; and controlling the optical transceiver based on i) a transmitter clock signal generated by a transmitter phase-locked loop (PLL) using the reference clock signal, and ii) a receiver clock signal generated by a receiver PLL using the reference clock signal.

The present invention relates to the field of radio frequency measurement technology, and discloses a broadband pulse measurement method based on a vector network analyzer. Aiming at the problem that the device under test cannot withstand long-term high-power signals, a special measurement scheme is designed for the vector network analyzer. The radio frequency source signal is modulated by a pulse switch, and the signal is down-converted to an intermediate frequency after passing through the device under test, and the intermediate frequency is then pulse modulated and filtered. A pulse modulation source is designed for radio frequency and intermediate frequency signal modulation and reception sampling synchronization to ensure that the sampling bandwidth is within the positive pulse width of the pulse period. When sampling, a reference pulse rising edge is introduced to trigger the digital down-conversion working state. After software delay, sampling is performed to achieve synchronization between sampling and intermediate frequency signal, and the results are accurate, stable and fast. In addition, in order to achieve distortion of the intermediate frequency signal link after radio frequency modulation, a modulation signal is introduced to further modulate and improve it. This scheme can effectively measure the amplitude-frequency characteristics, phase and other characteristics of the device under test.

The present invention provides a GTX high-speed data transmission method, device and equipment for a bad channel, comprising determining a 192-bit synchronization bit group, wherein the encoding of the synchronization bit group does not belong to the encoding of the payload data; inserting the 192-bit synchronization bit group between each payload data sent by the sending end; capturing the 192-bit synchronization bit group based on the exhaustive detection principle when the receiving end receives the payload data sent by the sending end; if the 192-bit synchronization bit group is captured, synchronization locking is performed, the 192-bit synchronization bit group is determined to be the starting position of the serial-to-parallel conversion, and data transmission is performed based on the starting position; if the 192-bit synchronization bit group is not captured, it is determined that a bad channel fails, and since the 192-bit synchronization bit group that does not belong to the payload data is used as the identifier of the starting position for identification, compared with simple binary identifier identification, the stability and accuracy of data transmission in the bad channel are guaranteed.

The present invention provides an effective hardware architecture for a combined aggregation and distribution unit (CCDU) ​​ORAN-compliant clock synchronizer module for 5G foundation applications required to handle L1, L2, and L3 schedules of the network. The CCDU design can achieve CU and DU functionality in a single unit and can operate over a wide temperature range. The single board approach of the CCDU makes the CCDU more reliable and less costly. The CCDU can support different types of synchronization and can provide site alarms over dry contacts for accommodating external alarm devices.

A communication system uses a differential edge modulation scheme having one of four or more values and a clock pulse is also encoded in each unit interval. A four-valued encoding may be as follows: prior to each unit interval, two signals are both at the same value; at the start of the unit interval, a first one of the signals is transitioned to indicate a first bit of the symbol; after a selected one of two delay periods that are less than the unit interval, the other signal is transitioned to indicate a second bit of the symbol; after this transition, both signals are again at the same value. The transitioning, at the start of the unit interval, provides an edge that may be extracted and used a timing reference.

Systems, methods, and circuits for performing bidirectional communication using an edge time in a signal are provided. In one example, a method involves receiving a common signal on a signal line between one device and another. The common signal comprises a series of signal periods, and each signal period includes a first edge of a first type and a second edge of a second type, different from the first type. In each signal period of the series of signal periods, information to be communicated by the other device is determined at least based on the determined time of the first edge, and a time for a subsequent second edge with respect to the signal period is determined based on information to be communicated to the other device.The subsequent second edge is generated at the selected time in a subsequent signal period of the series of signal periods.

A channel between quantum controller modules (e.g., pulse processors) is operable to communicate high speed data required for processing qubit states that may be distributed across a quantum computer. The latency of the communication channel is deterministic and controllable according to a system clock domain.

An HDMI signal can be transmitted and received in a high-speed serial communication method different from the HDMI. A communication device includes an encoder that generates a packet of a time division duplex (TDD) communication method including a high-definition multimedia interface (HDMI) signal, and a communication unit that transmits the packet to the communication partner device for each of a plurality of division periods obtained by dividing one TDD burst period in the TDD communication method.

Embodiments of this disclosure relate to communication using edge timing in signals. Systems, methods, and circuits are provided to perform bidirectional communication using edge timing. In an example, one method includes receiving a first signal on a first signal line, the first signal having a first timing edge and a first data edge. The first timing edge and the first data edge are of different types. The first data edge is an edge immediately adjacent to the first timing edge and occurs after a first elapsed time following the first timing edge. The method includes sampling the first signal for a predetermined sampling time after the first timing edge to determine a first data value. A second data value is determined, and a second signal having a second timing edge and a second data edge is generated. A second elapsed time between the second timing edge and the second data edge encodes the second data value. The second signal is transmitted on the second signal line.