25results about "Synchronisation transmitters" patented technology

A method of generating a synchronization signal comprises synchronizing, by a first wireless user device (410, 430, 440, 450, 460, 470, 900, 950), a timing of a synchronization signal received from a synchronization source, wherein the timing of the synchronization signal is associated with a synchronization timing of a Global Navigational Satellite System, GNSS, determining a subframe to transmit a primary sidelink synchronization signal, PSSS, and a secondary sidelink synchronization signal, SSSS, mapping the SSSS to two consecutive single frequency-frequency division multiple access, SC-FDMA, symbols in the determined subframe, and transmitting, from the first wireless user device to a second wireless user device, the PSSS and the SSSS in the determined subframe. The mapping the SSSS comprises generating a first length-31 sequence based on ml, generating a second length-31 sequence based on m0, where ml is greater than m0, and mapping, based on a first mapping scheme of two mapping schemes, the first length-31 sequence and the second length-31 sequence to 62 consecutive subcarriers in the two consecutive SC-FDMA symbols in the determined subframe, wherein a portion of the first length-31 sequence is mapped to a subcarrier having a lowest index among the 62 consecutive subcarriers and a portion of the second length-31 sequence is mapped to a subcarrier having a highest index among the 62 consecutive subcarriers.

The present invention provides an effective hardware architecture for a combined aggregation and distribution unit (CCDU) ​​ORAN-compliant clock synchronizer module for 5G foundation applications required to handle L1, L2, and L3 schedules of the network. The CCDU design can achieve CU and DU functionality in a single unit and can operate over a wide temperature range. The single board approach of the CCDU makes the CCDU more reliable and less costly. The CCDU can support different types of synchronization and can provide site alarms over dry contacts for accommodating external alarm devices.

A communication system uses a differential edge modulation scheme having one of four or more values and a clock pulse is also encoded in each unit interval. A four-valued encoding may be as follows: prior to each unit interval, two signals are both at the same value; at the start of the unit interval, a first one of the signals is transitioned to indicate a first bit of the symbol; after a selected one of two delay periods that are less than the unit interval, the other signal is transitioned to indicate a second bit of the symbol; after this transition, both signals are again at the same value. The transitioning, at the start of the unit interval, provides an edge that may be extracted and used a timing reference.

Systems, methods, and circuits for performing bidirectional communication using an edge time in a signal are provided. In one example, a method involves receiving a common signal on a signal line between one device and another. The common signal comprises a series of signal periods, and each signal period includes a first edge of a first type and a second edge of a second type, different from the first type. In each signal period of the series of signal periods, information to be communicated by the other device is determined at least based on the determined time of the first edge, and a time for a subsequent second edge with respect to the signal period is determined based on information to be communicated to the other device.The subsequent second edge is generated at the selected time in a subsequent signal period of the series of signal periods.

[Problem] To provide a communication device and a communication system that perform serial communication at low power and at high speed. [Solution] The communication device comprises: a state-switching control unit for controlling switching between a first state that establishes synchronization for performing communication with a communication partner device, a second state that initiates communication after synchronization is established in the first state, a third state that causes communication to be intermittently stopped without losing the establishment of synchronization, and a fourth state that reestablishes synchronization with the communication partner device when communication is resumed after being stopped for a longer period than in the third state; a first communication control unit for repeating, on a first cycle, the operation of continuously transmitting a first signal within a first signal interval to the communication partner device when in the fourth state; a second communication control unit which, when a second signal outputted from the communication partner device in response to the first signal is received, transmits a third signal that is synchronized to the second signal to the communication partner device. The switching control unit causes transition from the fourth state to the first state when the second communication control unit transmits the third signal.

The application provides a serial transceiver-based data transmission method, a transceiver, a medium and equipment, and the method comprises the following steps: a serial transceiver switches clock frequency in the process of transmitting frame data, sends clock frequency switching information to a sending end parallel-serial conversion unit, and repeatedly writes current frame data into a sending data buffer; the sending end parallel-serial conversion unit reads parallel valid data of a preset bit number in the current frame data, counts the read bit number through a counter, and after receiving the clock frequency switching information, judges whether the count value is equal to the preset bit number value; if yes, it is determined that the parallel valid data is serialized, and serial data is obtained; the receiving end serial-parallel conversion unit converts the serial data into parallel data, and after detecting a frame header in the parallel data, it is determined that the frame header is in the aligned frame data, and the frame data is written into a receiving data buffer. The application realizes switching of data transmission rate of the serial transceiver in the data transmission process.

The invention provides a synchronization method, a synchronization device, and a transceiver device for multi-channel data transmission. The synchronization method transmits test data to N receiving devices, obtains a transmission cycle and N delayed playback timestamps based on the information fed back by the receiving devices, the data packet preparation time, a first time, and a predetermined error tolerance time; transmits audio data packets to the N receiving devices, obtains an existing data playback duration and a time difference based on the acknowledgment packets fed back by the receiving devices; adjusts the predetermined error tolerance time to a target error tolerance time according to the comparison result between the time difference and a predetermined time difference threshold. This achieves real-time and timely adjustment of the delayed playback time of audio data packets according to the actual situation of data transmission, thereby achieving the purpose of audio synchronization in multi-channel wireless transmission.

The invention discloses a communication system, a communication method, a host computer, a slave computer and a device with master-slave communication, the communication system comprises the host computer and at least one slave computer, and the host computer is in communication connection with the at least one slave computer for data interaction; the host sends host data, the data frame format of the host data comprises a frame type selection bit, the value of the frame type selection bit represents a target state machine of a target slave selected by the host, and the target slave is a slave which performs data interaction with the host in the at least one slave. According to the communication system and method, the data processing amount of the target slave can be reduced, and the data processing efficiency of the slave is improved.

The application provides a signal sampling time determination method, device and terminal equipment, and relates to the technical field of communication. The signal sampling time determination method comprises the following steps: obtaining a signal estimation error in a first sampling interval; the first sampling interval is an interval between a first signal sampling time and a second signal sampling time; obtaining a signal sampling error threshold of a second sampling interval according to the signal estimation error in the first sampling interval and a time length of the first sampling interval; determining a third signal sampling time according to the signal sampling error threshold of the second sampling interval and a first sampling signal sent at the second signal sampling time; the second sampling interval is an interval between the second signal sampling time and the third signal sampling time; and the second signal sampling time is located before the third signal sampling time. The signal sampling time obtained in the application is used for sending a sampling signal, which can reduce a signal estimation error obtained by terminal signal estimation and increase the accuracy of estimated signal state information.

Technologies for a jitter injection generator and a spectrum hardware engine for measuring and assessing phase noise and jitter transfer function are described. One communication device includes a timing and synchronization circuit that generates a signal with time-domain data, and a spectrum hardware engine. The spectrum hardware engine converts this data into frequency-domain data. It has registers storing past outputs, multipliers for computing products using these values and a pre-computed coefficient, and a summation block for combining the current input with these products to get the current output. This output is sent to the computing device to estimate phase noise.

A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes performing a link equalization operation, checking a transmission mode of the interface device, and determining a transmission parameter of the interface device based on a status of the first elastic buffer or a status of a second elastic buffer included in another interface device communicating with the interface device when the transmission mode is a transmission parameter adjustment mode.

In one embodiment, a method comprises identifying at a first powered device in communication with power sourcing equipment, a second powered device in communication with the first powered device, wherein the first powered device is receiving high voltage pulse power from the power sourcing equipment, notifying the power sourcing equipment of the second powered device at the first powered device, and performing a low voltage power initialization at the first powered device with the second powered device before passing the high voltage pulse power to the second powered device. The first powered device comprises a local isolation switch for a first low voltage pulse power initialization with the power sourcing equipment at start-up of the first powered device and for receiving the high voltage pulse power from the power sourcing equipment and an output isolation switch for said low voltage power initialization with the second powered device and for passing the high voltage pulse power to the second powered device.

This invention relates to the field of industrial automation data aggregation and remote transmission technology, specifically a multi-node data aggregation and remote transmission system for temperature transmitters. It includes: a clock generation unit for periodically broadcasting a clock signal without address information to announce the start of a data encoding cycle; at least one asynchronous pulse encoding unit for responding to the clock signal, autonomously encoding its node identity information and temperature data into a single asynchronous time-series encoded pulse relative to the clock signal, and sending it to a shared channel; and an asynchronous time-series pattern recognition unit for passively listening to and receiving asynchronous time-series encoded pulses on the shared channel, using the clock signal as a reference. This invention resolves the contradiction of long-term, ineffective consumption of large amounts of computing resources to cope with low-probability sudden events, and breaks the rigid constraint between risk identification accuracy and system response timeliness.

The embodiment of the invention discloses a data processing device and a data driving device, and the data processing device comprises a first data mapping part which converts original data into a plurality of data packets; and an encoder that inverts a portion of bits of the plurality of packets; the encoder includes: a data comparison section that compares a most significant bit (MSB) of a first packet and a least significant bit (LSB) of a second packet adjacent to each other among a plurality of packets; a code conversion unit that, when the most significant bit of the first packet and the least significant bit of the second packet are the same, inverts the least significant bit of the second packet; and a bit generation unit that generates an instruction packet in which conversion information for the least significant bit of the second packet is stored.

A network node including a physical layer transceiver (106) and a physical layer transceiver. The transceiver includes a media independent interface (200), a converter circuit block (210) including circuit elements (214) configured to convert digital signals to analog signals for transmission over a network communication medium and to convert analog signals received over the medium to digital signals, and one or more processing blocks (202A, 202B, 202C) configured to process digital data communicated between the media independent interface and the converter circuit block in accordance with a network protocol. A management and control circuit element (220) including power management circuit elements and reset circuit elements is provided. The transceiver further includes at least one single event effect (SEE) monitor (240), such as an environmental monitor (242), a configuration register monitor (244), a state machine monitor (246), or a phase locked loop (PEL) lock monitor (250) configured to detect and respond to SEE events in the transceiver.

The embodiment of the invention discloses a data synchronization method, device and system. In a scene of synchronizing data streams of a physical layer, the synchronization process of the data streams can be timed. Furthermore, whether the data stream with the time length meeting the timeout condition exists in the synchronization process is judged, which is equivalent to whether the situation that the synchronization time is too long exists. If the condition that the synchronization time is too long exists, it is indicated that a system fault or link deterioration may occur, then corresponding timeout processing, such as error reporting and system resetting, needs to be carried out, so that the system fault or link deterioration can be dealt with in time, and the data transmission efficiency is optimized.

Systems and techniques are provided for an autonomous vehicle (AV) to select a mobile network. An example method can include establishing a connection between the AV and a mobile device associated with a passenger of the AV; identifying, using the connection, a first mobile network associated with the mobile device; determining that the first mobile network associated with the mobile device is different than a second mobile network associated with the AV; determining, based on a first network indicator associated with the first mobile network and a second network indicator associated with the second mobile network, that the first mobile network is preferable to the second mobile network; and initiating a mobile connection between the AV and the first mobile network.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

A signal transmitting method, an electronic device, and a communication system are provided. The signal transmitting method comprises: transmitting, by a transmitting terminal, a DQ redundancy code and a DQS preamble code to a receiving terminal during a preamble period, the DQ redundancy code is configured with a specific pattern such that jitter of a DQ signal tracks jitter of a DQS signal, and when the DQ redundancy code has the specific pattern, the lowest n bits of a pattern of the DQ redundancy code match the lowest n bits of a pattern of the DQS preamble code, where n is an integer greater than or equal to two; transmitting, by the transmitting terminal, the DQ signal and the DQS signal to the receiving terminal during a data transmission period. The signal transmitting method of the present disclosure helps to reduce timing loss.

The invention relates to the technical field of wireless communication, in particular to a DMF (Dimethyl Formamide)-based peak-to-average ratio tracking adaptive threshold detection method and device and a medium, and the method comprises the following steps: transmitting a data frame containing two sections of same synchronization sequences, and carrying out correlation operation at a receiving end by using a digital matched filter; an absolute threshold capable of being dynamically updated is set for preliminary screening, and correlation values exceeding the threshold are continuously stored; calculating peak-to-average ratios of correlation values in the window, and if continuous peak-to-average ratios are greater than a relative threshold, judging that an effective peak value is captured and updating an absolute threshold; synchronous capturing is completed through tracking detection and double-peak position verification. According to the method, the threshold self-adaptive adjustment under the resource limited condition is realized, and the detection probability and the system stability under the low signal-to-noise ratio environment are remarkably improved.

The circuits and methods described herein provide technical solutions for technical problems facing USB links. To reduce or eliminate effects associated with a USB link entering a low-power mode, initial link acquisition may be performed while the spread-spectrum-clocking (SSC) modulation is disabled. Following the initial link acquisition, the SSC modulation may be enabled dynamically in a later stage. This delayed enablement of the re-timers provides improved performance over solutions in which the SSC modulation is constantly enabled, including reducing the complexity of the timing training process and enabling a faster USB link re-establishment. This reduced link acquisition period may enable the system to enter power saving modes more frequently, and may reduce latency involved in exiting power saving modes. This may maintain or improve total USB transmission speeds and may reduce USB-related power consumption for USB connected devices.

The invention discloses a variable time delay system, which comprises a transceiving unit, a data processing unit, an upper computer, a clock unit and a local oscillation unit, the transmitting-receiving unit comprises a plurality of transmitting-receiving sub-circuits, each transmitting-receiving sub-circuit comprises a first transmitting-receiving sub-module and a second transmitting-receiving sub-module, and each of the first transmitting-receiving sub-module and the second transmitting-receiving sub-module comprises a radio frequency transmitting circuit and a radio frequency receiving circuit; the radio frequency receiving circuit of the first transceiving sub-module receives signals, inputs the signals into the data processing unit for time delay and frequency offset processing, and then sends the signals to the radio frequency transmitting circuit of the second transceiving sub-module, and the radio frequency receiving circuit of the second transceiving sub-module receives signals, inputs the signals into the data processing unit for time delay and frequency offset processing. The radio frequency transmitting circuit is used for transmitting the signals to the first transmitting-receiving sub-module; the clock unit provides a clock signal; the local oscillator unit provides a local oscillator signal for the transceiver unit; and the upper computer is connected with the transceiving unit, the clock unit and the data processing unit to control the whole system to work. According to the invention, the compatibility of the whole time delay system for processing radio frequency signals is improved.

The present disclosure provides a metastability detector and a calibration method for synchronous data transfer in distributed synchronous systems. The metastability detector integrates hardware adapted to, for reference signal patterns sent from first transceiver device to a second transceiver device, determine a metastability value based on deviations from the 50% duty cycle. The calibration method adjusts clock phases of generated signal patterns based on metastability values determined by measuring deviations from the 50% duty cycle. The example embodiments of the present disclosure provide reliable, high-speed data transfer with minimal synchronization issues in distributed synchronous systems. The metastability detector and calibration method may further account for variations over time and may maintain optimal performance of data transfer in distributed synchronous systems.

Adaptive clock mechanisms for serial links utilizing a delay-chain-based edge generation circuit to generate a clock that is a faster (higher-frequency) version of an incoming digital clock. The base frequency of the link clock utilized by the line transmitters is determined by the (slower) clock utilized by the digital circuitry supplying data to the line transmitters. An edge generator that may be composed of only non-synchronous circuit elements multiplies the edges of the slower clock to generate the link clock and also a clock forwarded to the receiver at a phase offset from the link clock.

To reduce circuit complexity and reduce chip packaging and wiring.SOLUTION: A method of decoding a single-channel communication includes the steps of: generating a low level of a clock signal based on a high level of a long- and short-code signal; generating a delay pulse signal based on the long- and short-code signal, a delay time length of the delay pulse signal being a half of a clock period; generating a high level of the clock signal based on the delay pulse signal; and generating a digital signal based on the clock signal and the long- and short-code signal. The decoding method simultaneously decodes a clock signal and a data signal.SELECTED DRAWING: Figure 13