78results about "Synchronisation transmitters" patented technology

A retimer and a retiming method may employ dual path clock forwarding to drive a transmit clock generator. An illustrative integrated retimer circuit includes a sampling element configured to generate a digital receive signal by sampling an analog receive signal in accordance with a sampled signal; a timing error estimator configured to generate a timing error signal indicative of an estimated timing error of the sampled signal relative to the analog received signal; a clock recovery circuit configured to derive a sampled signal from the estimated timing error and a reference clock in part by determining the frequency signal; a transmitter configured to retransmit the digital reception signal according to a transmission clock; and a transmit clock generator configured to derive a transmit clock. The transmit clock generator operates based on each of: a reference clock; a frequency signal; and a phase error of the transmit clock with respect to the sampled signal.

Some embodiments include apparatuses and methods using a clock generator to generate clock signals, the clock signals being out of phase with each other; a transmitting circuit to provide patterns of data at an output of the transmitting circuit responsive to timing of the clock signals; and calculation and control circuitry to calculate an integral nonlinearity vector that represents offsets of transitions of the patterns from respective target positions, and to generate control information based on the integral nonlinearity vector to adjust phases of the clock signals based on the control information.

Retimers and retiming methods may employ dual path clock forwarding to drive a transmit clock generator. One illustrative integrate retimer circuit includes: a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with a sampling signal; a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; a clock recovery circuit configured to derive the sampling signal from the estimated timing error and a reference clock in part by determining a frequency signal; a transmitter configured to retransmit the digital receive signal in accordance with a transmit clock; and a transmit clock generator configured to derive the transmit clock. The transmit clock generator operates based on each of: the reference clock; the frequency signal; and a phase error of the transmit clock relative to the sampling signal.

The embodiment of the invention discloses a data synchronization method, device and system. In a scene of synchronizing data streams of a physical layer, the synchronization process of the data streams can be timed. Furthermore, whether the data stream with the time length meeting the timeout condition exists in the synchronization process is judged, which is equivalent to whether the situation that the synchronization time is too long exists. If the condition that the synchronization time is too long exists, it is indicated that a system fault or link deterioration may occur, then corresponding timeout processing, such as error reporting and system resetting, needs to be carried out, so that the system fault or link deterioration can be dealt with in time, and the data transmission efficiency is optimized.

A dual-mode transmitter for a low-power double-data rate (LPDDR) interface can be operated in one of a non-return to zero (NRZ) mode and a pulse amplitude modulation (PAM)-4 mode. The dual-mode transmitter includes: a pseudorandom binary sequence (PRBS) generator configured to generate a transmission signal to be transmitted to a dual-mode receiver; at least one serializer configured to serialize the transmission signal; a single-ended to differential (S2D) configured to convert the serialized transmission signal in a form of a single-ended signal into a differential signal; a ZQ calibration configured to generate a result code for matching an impedance value at an output terminal of the dual-mode transmitter with a terminating resistance value of the dual-mode receiver; and a pre-driver configured to combine the differential signal obtained by the converting and the result code.

The present invention provides an efficient hardware architecture for an ORAN compliant clock synchronizer module of a combined centralized unit and a distributed unit (CCDU) for a 5G basement application required for processing L1, L2 and L3 scheduling of the network. The CCDU design may provide the functionality of a CU and a DU with single unit and can operate over wide temperature range. A single board approach of the CCDU make the CCDU more reliable and less costly. The CCDU can support different kinds of synchronization and can provide site alarms over dry contacts to equip with external alarm device.

A method of generating a synchronization signal comprises synchronizing, by a first wireless user device (410, 430, 440, 450, 460, 470, 900, 950), a timing of a synchronization signal received from a synchronization source, wherein the timing of the synchronization signal is associated with a synchronization timing of a Global Navigational Satellite System, GNSS, determining a subframe to transmit a primary sidelink synchronization signal, PSSS, and a secondary sidelink synchronization signal, SSSS, mapping the SSSS to two consecutive single frequency-frequency division multiple access, SC-FDMA, symbols in the determined subframe, and transmitting, from the first wireless user device to a second wireless user device, the PSSS and the SSSS in the determined subframe. The mapping the SSSS comprises generating a first length-31 sequence based on ml, generating a second length-31 sequence based on m0, where ml is greater than m0, and mapping, based on a first mapping scheme of two mapping schemes, the first length-31 sequence and the second length-31 sequence to 62 consecutive subcarriers in the two consecutive SC-FDMA symbols in the determined subframe, wherein a portion of the first length-31 sequence is mapped to a subcarrier having a lowest index among the 62 consecutive subcarriers and a portion of the second length-31 sequence is mapped to a subcarrier having a highest index among the 62 consecutive subcarriers.

Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

Frequency error tracking and lane monitoring techniques for multi-lane optical transceivers are provided. In one aspect, a method includes capturing phase and frequency information recovered by clock-and-data recovery circuits from data traveling along a plurality of lanes of an optical transceiver, with one of the lanes being a master lane; determining a frequency error based on the phase and frequency information of the master lane; outputting, by a tunable oscillator, a reference clock based on the frequency error; and controlling the optical transceiver based on i) a transmitter clock signal generated by a transmitter phase-locked loop (PLL) using the reference clock signal, and ii) a receiver clock signal generated by a receiver PLL using the reference clock signal.

The present invention relates to the field of radio frequency measurement technology, and discloses a broadband pulse measurement method based on a vector network analyzer. Aiming at the problem that the device under test cannot withstand long-term high-power signals, a special measurement scheme is designed for the vector network analyzer. The radio frequency source signal is modulated by a pulse switch, and the signal is down-converted to an intermediate frequency after passing through the device under test, and the intermediate frequency is then pulse modulated and filtered. A pulse modulation source is designed for radio frequency and intermediate frequency signal modulation and reception sampling synchronization to ensure that the sampling bandwidth is within the positive pulse width of the pulse period. When sampling, a reference pulse rising edge is introduced to trigger the digital down-conversion working state. After software delay, sampling is performed to achieve synchronization between sampling and intermediate frequency signal, and the results are accurate, stable and fast. In addition, in order to achieve distortion of the intermediate frequency signal link after radio frequency modulation, a modulation signal is introduced to further modulate and improve it. This scheme can effectively measure the amplitude-frequency characteristics, phase and other characteristics of the device under test.

The present invention provides an effective hardware architecture for a combined aggregation and distribution unit (CCDU) ​​ORAN-compliant clock synchronizer module for 5G foundation applications required to handle L1, L2, and L3 schedules of the network. The CCDU design can achieve CU and DU functionality in a single unit and can operate over a wide temperature range. The single board approach of the CCDU makes the CCDU more reliable and less costly. The CCDU can support different types of synchronization and can provide site alarms over dry contacts for accommodating external alarm devices.

A communication system uses a differential edge modulation scheme having one of four or more values and a clock pulse is also encoded in each unit interval. A four-valued encoding may be as follows: prior to each unit interval, two signals are both at the same value; at the start of the unit interval, a first one of the signals is transitioned to indicate a first bit of the symbol; after a selected one of two delay periods that are less than the unit interval, the other signal is transitioned to indicate a second bit of the symbol; after this transition, both signals are again at the same value. The transitioning, at the start of the unit interval, provides an edge that may be extracted and used a timing reference.

Systems, methods, and circuits for performing bidirectional communication using an edge time in a signal are provided. In one example, a method involves receiving a common signal on a signal line between one device and another. The common signal comprises a series of signal periods, and each signal period includes a first edge of a first type and a second edge of a second type, different from the first type. In each signal period of the series of signal periods, information to be communicated by the other device is determined at least based on the determined time of the first edge, and a time for a subsequent second edge with respect to the signal period is determined based on information to be communicated to the other device.The subsequent second edge is generated at the selected time in a subsequent signal period of the series of signal periods.

A channel between quantum controller modules (e.g., pulse processors) is operable to communicate high speed data required for processing qubit states that may be distributed across a quantum computer. The latency of the communication channel is deterministic and controllable according to a system clock domain.

Embodiments of this disclosure relate to communication using edge timing in signals. Systems, methods, and circuits are provided to perform bidirectional communication using edge timing. In an example, one method includes receiving a first signal on a first signal line, the first signal having a first timing edge and a first data edge. The first timing edge and the first data edge are of different types. The first data edge is an edge immediately adjacent to the first timing edge and occurs after a first elapsed time following the first timing edge. The method includes sampling the first signal for a predetermined sampling time after the first timing edge to determine a first data value. A second data value is determined, and a second signal having a second timing edge and a second data edge is generated. A second elapsed time between the second timing edge and the second data edge encodes the second data value. The second signal is transmitted on the second signal line.

A slave node calculates and stores a propagation delay generated when exchanging a message with a master node. The master node transmits a reference time indicated by a hardware clock of the master node, and the slave node synchronizes a hardware clock of the slave node to the reference time indicated by the hardware clock of the master node. The master node transmits a time value in a first time domain to the slave node, where the time value is calculated by the master node by adding an offset of the first time domain to the reference time. The slave node calculates the offset using the time value and the stored propagation delay, and obtains a time in the first time domain by applying the calculated offset to a reference time indicated by the hardware clock of the slave node.

[Problem] To provide a communication device and a communication system that perform serial communication at low power and at high speed. [Solution] The communication device comprises: a state-switching control unit for controlling switching between a first state that establishes synchronization for performing communication with a communication partner device, a second state that initiates communication after synchronization is established in the first state, a third state that causes communication to be intermittently stopped without losing the establishment of synchronization, and a fourth state that reestablishes synchronization with the communication partner device when communication is resumed after being stopped for a longer period than in the third state; a first communication control unit for repeating, on a first cycle, the operation of continuously transmitting a first signal within a first signal interval to the communication partner device when in the fourth state; a second communication control unit which, when a second signal outputted from the communication partner device in response to the first signal is received, transmits a third signal that is synchronized to the second signal to the communication partner device. The switching control unit causes transition from the fourth state to the first state when the second communication control unit transmits the third signal.

A first communication device receives an analog receive signal over a communication medium. An ADC of the first communication device converts the analog receive signal into a digital receive signal. Logic circuitry of the first communication device detects a plurality of timing signals from a second communication device based on an analysis of the digital receive signal. The logic circuitry adjusts a sampling phase of the ADC in association with at least some of the timing signals such that the ADC uses different sampling phases when different ones of the timing signals are detected. The logic circuitry determines timing information based on the detection of the plurality of timing signals when the ADC uses different sampling phases when different ones of the timing signals are detected.The first communication device determines a propagation time between the first communication device and the second communication device based on the timing information.

A method for reclocking an input signal, the method comprising the following steps: - receiving a digital data stream with an average data rate corresponding to a first clock rate; - receiving a clock signal having a second clock rate from an adjustable clock source; and - adjusting a clock edge timing of transitions within the digital data stream based on the clock signal to generate a modulated output signal having a power spectrum, wherein the rising and falling clock edges of the digital data stream are re-clocked such that the power spectrum of the modulated output signal includes spectral zeros at the second clock frequency and at multiples of the second clock frequency without changing the average data rate.

The invention discloses a data sending method and device, computer equipment and a storage medium, and relates to the technical field of data transmission, and the method comprises the step of dynamically adjusting the data transmission frequency according to the signal states of two clock domains. And if the receiving bandwidth of the first interface is relatively low, when it is detected that the signal values of the synchronous effective signal and the second effective signal at the target moment are different, the second interface stops sending data, so that the transmission frequency is reduced, the bandwidth requirement of the first interface is met, and data loss is avoided. On the contrary, if the receiving bandwidth of the first interface is high, when the signal values of the synchronous effective signal and the second effective signal at the target moment are the same, the second interface can perform data transmission. According to the technical scheme, the bandwidth of the second interface can be dynamically adjusted to be matched with the bandwidth of the first interface, bandwidth differences of different interfaces can be adapted, data transmission is more stable, and flexible bandwidth matching is achieved.

A network interface device includes packet processing circuity to capture a network packet transmitted by a software application running on a computing device and capture, at time of transmission of the network packet, a value of a physical clock as a receive timestamp for subscriber entities of the computing device. The circuitry associates the receive timestamp with a first packet copy of the network packet and inserts the first packet copy to a first receive pipeline of a first subscriber entity. The circuitry associates the receive timestamp with a second packet copy of the network packet and inserts the second packet copy to a second receive pipeline of a second subscriber entity.

There is provided a reception device including a data signal receiver circuit, a clock signal receiver circuit, and a discrimination circuit. The data signal receiver circuit receives a data signal through a data signal line, and receives a data blanking signal through the data signal line in a blanking period of the data signal. The clock signal receiver circuit receives a clock signal and a clock blanking signal through a clock signal line, the clock blanking signal outputted in synchronization with the blanking period of the data signal. The discrimination circuit discriminates communication modes on a basis of one or both of a signal value of the data blanking signal and a signal value of the clock blanking signal.

The application provides a serial transceiver-based data transmission method, a transceiver, a medium and equipment, and the method comprises the following steps: a serial transceiver switches clock frequency in the process of transmitting frame data, sends clock frequency switching information to a sending end parallel-serial conversion unit, and repeatedly writes current frame data into a sending data buffer; the sending end parallel-serial conversion unit reads parallel valid data of a preset bit number in the current frame data, counts the read bit number through a counter, and after receiving the clock frequency switching information, judges whether the count value is equal to the preset bit number value; if yes, it is determined that the parallel valid data is serialized, and serial data is obtained; the receiving end serial-parallel conversion unit converts the serial data into parallel data, and after detecting a frame header in the parallel data, it is determined that the frame header is in the aligned frame data, and the frame data is written into a receiving data buffer. The application realizes switching of data transmission rate of the serial transceiver in the data transmission process.

The invention provides an artificial cochlea signal synchronization device and a debugging method, and the device comprises an artificial cochlea in-vitro all-in-one machine which is used for working after receiving a debugging instruction, and synchronously transmitting an optical signal; a standard implant; the separation equipment is used for detecting the induction current of the output end of the standard implant and sending a sending signal to the signal receiving synchronization equipment after detecting the current; the signal receiving synchronization equipment is used for sending a debugging instruction to the all-in-one machine, receiving an optical signal and a delivery signal and carrying out calculation processing when being in a calibration mode; and when in the debugging mode, the optical transceiver is used for sending a debugging instruction to the all-in-one machine, receiving an optical signal and sending a synchronizing signal to the medical professional detection equipment. The optical signal transmitter is additionally arranged in the artificial cochlea in-vitro all-in-one machine, then the signal synchronization device is matched, the synchronized signals are output to other medical devices for use, and the problem that the medical devices cannot be used for adjusting an existing artificial cochlea in-vitro all-in-one machine is solved.

A multi-chip package includes first and second groups of integrated circuit (IC) chips and a transfer IC chip disposed in the multi-chip package. The transfer IC chip is communicatively interposed between the first and second groups of IC chips and is configured to transfer signals from at least a first IC chip of the first group of IC chips to at least a second IC chip of the second group of IC chips or an output interface. The output interface is configured to output first data from the multi-chip package. A first set of ultra-short reach (USR) signaling links connects the first group of IC chips to the transfer IC chip. A second set of USR signaling links connects the second group of IC chips to the transfer IC chip. Each of the USR signaling links comprises a trace length of less than one inch.

The invention provides a synchronization method, a synchronization device, and a transceiver device for multi-channel data transmission. The synchronization method transmits test data to N receiving devices, obtains a transmission cycle and N delayed playback timestamps based on the information fed back by the receiving devices, the data packet preparation time, a first time, and a predetermined error tolerance time; transmits audio data packets to the N receiving devices, obtains an existing data playback duration and a time difference based on the acknowledgment packets fed back by the receiving devices; adjusts the predetermined error tolerance time to a target error tolerance time according to the comparison result between the time difference and a predetermined time difference threshold. This achieves real-time and timely adjustment of the delayed playback time of audio data packets according to the actual situation of data transmission, thereby achieving the purpose of audio synchronization in multi-channel wireless transmission.

Disclosed are methods and systems for a synchronizer system including a global positioning system (GPS) and a boundary clock. The method includes: generating, by the GPS of the synchronizer system, a first clock signal having a first predefined frequency; locking the first clock signal generated by the GPS at the first predefined frequency; and generating, by the boundary clock of the synchronizer system, a second clock signal having a second predefined frequency, to provide the second clock signal to a combined centralized and distributed unit (CCDU) system.

The invention discloses a communication system, a communication method, a host computer, a slave computer and a device with master-slave communication, the communication system comprises the host computer and at least one slave computer, and the host computer is in communication connection with the at least one slave computer for data interaction; the host sends host data, the data frame format of the host data comprises a frame type selection bit, the value of the frame type selection bit represents a target state machine of a target slave selected by the host, and the target slave is a slave which performs data interaction with the host in the at least one slave. According to the communication system and method, the data processing amount of the target slave can be reduced, and the data processing efficiency of the slave is improved.

The invention discloses an open-closed loop adaptive parallel timing synchronization device for echo high-speed data transmission signals, and belongs to the field of echo high-speed data transmission. The device comprises a digital parallel down converter, a digital parallel resampler, a digital parallel resampler, a digital parallel matched filter, a digital parallel matched filter and an open-closed loop self-adaptive parallel timing synchronizer. According to the invention, a full-digital parallel signal processing flow is adopted, so that the signal processing rate is effectively improved.

Various example embodiments relate to partial data transmission. A transmitter may receive at least one dataset for transmission. The dataset may be one of a plurality of datasets known to the transmitter and a receiver or to be signaled to the receiver. The transmitter may determine a first portion of the dataset. The size of the first portion may be determined based on a battery level indicator, a latency level associated with the dataset, a radio condition, or a network load. The receiver may recognize the dataset based on the first portion and / or at least one second portion transmitted by the transmitter. Apparatuses, methods, and computer programs are disclosed.