21 results about "Numeral system" patented technology

The application relates to a short link generation method and a related device, wherein the method comprises the following steps: obtaining an input long link and corresponding agency parameters; generating a first short link corresponding to the agency parameters according to a preset short link generation table; obtaining a second short link corresponding to the long link by incrementing the first short link; converting the second short link to obtain a third short link in a target numeral system, and storing the third short link and the long link together in a short link mapping table in a database; and generating a short link corresponding to the long link based on the short link mapping table. The application generates a first short link corresponding to the agency parameters by inputting a long link and the agency parameters corresponding to the long link, obtains a second short link by incrementing the first short link, converts the second short link to obtain a third short link, and finally generates a short link based on the short link mapping table, so that the length of the address corresponding to the long link can be simplified, the conversion and access efficiency of the long link can be improved, the effectiveness and security of the long link can be improved, and maintenance is facilitated.

An integrated circuit includes a hardware inexact floating-point logarithmic number system (FPLNS) multiplier. The integrated circuit access registers containing a first floating-point binary value and its first logarithmic binary value and a second floating-point binary value and its second logarithmic binary value, each being in an FPLNS data format. The FPLNS multiplier configured to multiply the first and second floating-point binary values by adding the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shifting a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtracting a correction factor from the first shifted bias value to form a first corrected bias value, and subtracting the first corrected bias value from the first logarithmic sum to form a first result.

The invention describes a process for exchanging data / information using sine waves, the process comprising the steps of: transmitting and receiving data using encoded sine waves; wherein the coding comprises the following sub-steps: creating a working environment; a digital system of which the cardinal number is higher than the cardinal number 2 of the binary code is adopted; defining and classifying symbols of the adopted digital system by using a symbol classification method; generating a geometric waveform via a mathematical function; changing the amplitude of each sine wave moment by moment; forming a point by amplitude variation; creating an array, wherein each symbol is associated with a corresponding numerical value; and using the array as a type constructor function.

The invention discloses a coding method for reducing power consumption of a feed-forward equalizer, and relates to the technical field of equalizer coding, and the coding method is characterized in that each bit is only a value {-1, 0, + 1}; adjacent bits cannot be non-zero at the same time; a first non-zero bit symbol from a high bit to a low bit must be consistent with the overall symbol; the code decomposes the input data into a few symbolized weight bits, and multiplication of the input data and the weight can be converted into shift and addition or subtraction operation. Therefore, for a single tap, corresponding multiplication operation can be realized through shifting and addition or subtraction, and final output can be obtained through summation finally. According to the invention, equivalent multiplication can be completed through a limited number of shift and addition; during implementation, a multiplier is not needed, only symbol control addition is needed, and a very efficient digital system is achieved through the encoding mode and is used for achieving multiplication, especially on occasions needing high throughput rate and low delay.

Methods, systems, and devices for wireless communications are described. In some examples, a first device may generate and transmit multiple shaped symbols based on a state for each shaped symbol. To generate each shaped symbol, the first device may normalize the state for each symbol in accordance with a range interval. If the state is outside the range interval, the first device may receive and convert bits from a bit buffer to generate the shaped symbol and normalize the state to be within the range interval. A second device may receive the multiple shaped symbols and generate information bits for each shaped symbol. Once the second device has received all of the shaped symbols of the sequence of shaped symbols, the second device may obtain a deshaped information vector based on the information bits generated for each shaped symbol and a state for a last shaped symbol.

Certain aspects of the present disclosure provide techniques for receiving a communication; decoding the communication to obtain a symbol sequence that is associated with a non-uniform probabilistic shaping distribution; performing a plurality of operations of asymmetric numeral system (ANS) encoding on a reverse symbol sequence derived from the symbol sequence, wherein a first operation of the plurality of operations uses a first probability parameter and a first symbol of the reverse symbol sequence, and wherein a second operation of the plurality of operations uses a second probability parameter and a second symbol of the reverse symbol sequence that occurs after the first symbol of the reverse symbol sequence; and obtaining a binary sequence in accordance with the ANS encoding.

Certain aspects of the present disclosure provide techniques for receiving a communication; decoding the communication to obtain a symbol sequence that is associated with a non-uniform probabilistic shaping distribution; performing a plurality of operations of asymmetric numeral system (ANS) encoding on a reverse symbol sequence derived from the symbol sequence, wherein a first operation of the plurality of operations uses a first probability parameter and a first symbol of the reverse symbol sequence, and wherein a second operation of the plurality of operations uses a second probability parameter and a second symbol of the reverse symbol sequence that occurs after the first symbol of the reverse symbol sequence; and obtaining a binary sequence in accordance with the ANS encoding.

The claimed technical solution relates to the field of protecting digital data displayed on the screen of an electronic device by using a digital watermarking mechanism. The technical result consists in providing a more effective method for protecting on-screen digital data by enhancing the robustness of digital watermarks during the generation of a protective layer. The claimed result is achieved by means of a computer-implemented method for protecting information displayed on the screen of a computing device, which is executed by a processor and comprises the steps of: generating a digital watermark in the form of a data block containing encoded information at least identifying the user of the computing device, wherein said information is encoded into a quaternary numeral system where each symbol from "0" to "3" is represented by a corresponding graphical element in the form of a line that lies at a given angle to an orthogonal coordinate axis, and the start of the data block is encoded as intersecting lines; generating a protective layer consisting of a set of data blocks and covering at least part of the display area of the screen of the computing device, wherein the colour and transparency of the digital watermark are determined; and applying the protective layer to the display area of the screen of the computing device.

An integrated circuit includes a hardware inexact floating-point logarithmic number system (FPLNS) multiplier. The integrated circuit access registers containing a first floating-point binary value and its first logarithmic binary value and a second floating-point binary value and its second logarithmic binary value, each being in an FPLNS data format. The FPLNS multiplier configured to multiply the first and second floating-point binary values by adding the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shifting a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtracting a correction factor from the first shifted bias value to form a first corrected bias value, and subtracting the first corrected bias value from the first logarithmic sum to form a first result.

A process for exchanging data / information using sine waves is described, comprising the steps of transmitting and receiving data using coded sine waves, the coding including the substeps of creating a working environment, incorporating a number system using a base greater than the base 2 of a binary code, defining and classifying symbols for the incorporated number system using a symbol classification method, generating geometric waveforms via numeric angle functions, sequentially varying the amplitude of each sine wave, forming points through amplitude variations, creating an array in which each symbol is associated with a corresponding numeric value, and using the array as a type constructor.

An integrated circuit includes a hardware inexact floating-point logarithmic number system (FPLNS) multiplier. The integrated circuit access registers containing a first floating-point binary value and its first logarithmic binary value and a second floating-point binary value and its second logarithmic binary value, each being in an FPLNS data format. The FPLNS multiplier configured to multiply the first and second floating-point binary values by adding the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shifting a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtracting a correction factor from the first shifted bias value to form a first corrected bias value, and subtracting the first corrected bias value from the first logarithmic sum to form a first result.

A computer-implemented method for automatically analyzing handwritten text to determine a mismatch between a purported writer and an actual writer is disclosed. The method comprises receiving two samples of digitized handwriting each allegedly created by one individual and received and entered into a digital system by another. The method further comprises performing a series of feature extractions to convert the samples into two vectors of extracted features; automatically clustering a set of vectors such that the first vector and the second vector are assigned to the same cluster among multiple clusters, based on vector similarity; and automatically determining that a same individual being associated with both the first and second samples indicates a heightened probability that the individual fraudulently created both samples. Finally, the method comprises automatically transmitting a message to flag additional samples of digitized handwriting entered into a digital system as possibly fraudulent.

An integrated circuit includes a hardware inexact floating-point logarithmic number system (FPLNS) multiplier. The integrated circuit access registers containing a first floating-point binary value and its first logarithmic binary value and a second floating-point binary value and its second logarithmic binary value, each being in an FPLNS data format. The FPLNS multiplier configured to multiply the first and second floating-point binary values by adding the first logarithmic binary value to the second logarithmic binary value to form a first logarithmic sum, shifting a bias constant by a number of bits of the mantissa of the first floating-point binary value to form a first shifted bias value, subtracting a correction factor from the first shifted bias value to form a first corrected bias value, and subtracting the first corrected bias value from the first logarithmic sum to form a first result.

Methods, systems, and devices for wireless communications are described. In some examples, a first device may generate and transmit multiple shaped symbols based on a state for each shaped symbol. To generate each shaped symbol, the first device may normalize the state for each symbol in accordance with a range interval. If the state is outside the range interval, the first device may receive and convert bits from a bit buffer to generate the shaped symbol and normalize the state to be within the range interval. A second device may receive the multiple shaped symbols and generate information bits for each shaped symbol. Once the second device has received all of the shaped symbols of the sequence of shaped symbols, the second device may obtain a deshaped information vector based on the information bits generated for each shaped symbol and a state for a last shaped symbol.

The present invention relates to introductory teaching timepieces in general and specifically to a novel design applicable to watches and clocks whereby only the second hand is present and from which the minute and hour hands have been removed. The second hand moves in equally timed units such that one full cycle of its motion consists of 60 equally timed seconds. In doing so, it isolates the sexagesimal basis for time-telling so that the beginner can understand this numerical system prior to combining it with the duodecimal system used for minutes and hours.

Proposed is a method in which all information transmitted over a system bus to and from a processor is represented in the form of multi-bit numbers, with each bit being represented in a binary positional numbering system, wherein each number in the system bus is represented in the form of a given n-bit number in a base-b positional numbering system; in each bit, each digit having one of the values in a range of from 0 to b -1 is represented by a k-bit number in a binary positional numbering system; each bit in this number is represented by an optical laser beam; each optical laser beam travels along a separate optically isolated optical fibre; together, all of the optically isolated optical fibres in each bit form a bit bundle; together, all of the bit bundles form a system bus. Also proposed are a computer and a computer network which operate on the above method. The advantage of the inventions is a decrease in the number of bits in data, address and command buses and thus a reduction in the number of data processing operations and therefore also the machine time as a result of an increase in the information content of each bit.

Exemplary embodiments of the present disclosure are directed towards a system and method for hardware-driven low-dimensional numerical representation for enhanced data compression, compact memory address representation, and efficient data indexing. The system introduces base-100 numeral structure known as Gole Number System, wherein each of 100 uniquely designed symbols maps to decimal value from 0 to 99. The system further supports compact memory address representation using extended base-128 symbol set called Evishta. Processor receives numerical input in decimal format, converts it into a base-100 representation using a Binary to Gole Converter (BCG), and maps each digit to corresponding Gole symbol. The encoded Gole symbols are stored in memory array optimized for space efficiency and retrieved for display rendering. A display unit renders the Gole symbols using reduced pixel dimensions per character, thereby minimizing pixel usage and reducing power consumption. The system is scalable across data storage, digital computation, memory representation, and user interface applications.

Methods, systems, and devices for wireless communications are described. In some examples, a first device may generate and transmit multiple shaped symbols based on a state for each shaped symbol. To generate each shaped symbol, the first device may normalize the state for each symbol in accordance with a range interval. If the state is outside the range interval, the first device may receive and convert bits from a bit buffer to generate the shaped symbol and normalize the state to be within the range interval. A second device may receive the multiple shaped symbols and generate information bits for each shaped symbol. Once the second device has received all of the shaped symbols of the sequence of shaped symbols, the second device may obtain a deshaped information vector based on the information bits generated for each shaped symbol and a state for a last shaped symbol.

Provided are methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. There is provided a method for encoding data into a beat that can be executed by a digital system to receive the data and construct the beat. The method includes assembling a plurality of words consecutively. The words include a first set of words in which each word has a length W, where W is the beat width. The words further include a second set of words in which each word has a length that is smaller or equal to W. The method further includes constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the words to form the beat.

According to various aspects, a computing device (100) is herein described. The computing device (100) is configured to determine a representation of a first number and a second number in a computing numeral system, the computing numeral system including a positional base system in which each position is associated with a numeral weight and a digit to represent a number in the computing numeral system, wherein the numeral weight is defined by a base of the positional base system and wherein each digit is associated with an amount of unique digit elements, wherein the amount of unique digit elements is greater by at least two than the base; and to execute one or more mathematical operations based on the first number and the second number in the computing numeral system and determining a computing result of the one or more mathematical operations in the computing numeral system.

As the maximum number of speed levels in a sound velocity meter increases, the number of musical pieces and other materials required also increases. Therefore, understanding the number of speed levels, which is determined by the number of superimposed musical pieces, becomes increasingly difficult as the number of levels increases. [Solution] The number of steps in the speed range of the sound velocity meter is changed from the usual decimal system to a positional numeral system of a lower value. By reducing the number of digits used in each digit of the new numeral system, the total number of musical pieces required is reduced, and consequently the maximum number of overlapping musical pieces is reduced, making it easier to understand the number of steps in the speed range by hearing.