7 results about "Performance tuning" patented technology

This invention discloses a software code optimization method and system based on big data. The method includes the following steps: constructing a code optimization knowledge base; acquiring the target code to be optimized and its corresponding estimated runtime data features; parsing the target code, extracting its structural features, and fusing the structural features with the estimated runtime data features to generate a target code fingerprint; performing similarity matching between the target code fingerprint and historical code fingerprints in the code optimization knowledge base to determine target historical code fingerprints that match the target code fingerprint; and determining a target optimization strategy for the target code based on the optimization strategy corresponding to the target historical code fingerprint. This invention can improve development efficiency, reducing the performance tuning work of senior architects, which can take hours or even days, to automated recommendations at the minute level, greatly improving software iteration efficiency.

This invention discloses a system performance optimization method and related equipment based on layered decoupling. When a kernel service node detects a cross-process service call, it obtains the call context information, filters target communication data that meets key service filtering conditions from the call context information to identify the current scenario and determine the current scenario identifier data. The hardware abstraction layer service performs performance parameter matching on the current scenario identifier data and performs business logic processing based on the parameter matching results to generate performance tuning data. The kernel service node then executes the performance optimization processing corresponding to the performance tuning data. This invention enables system performance optimization based on layered decoupling, significantly improving performance optimization efficiency. Through the layered decoupling architecture, it greatly reduces the difficulty and workload of code refactoring and adaptation, improves the maintainability and upgrade efficiency of the performance optimization framework, and can be widely applied in the field of system performance optimization technology.

This application provides a performance analysis method, apparatus, electronic device, chip, and medium, relating to the field of chip design and development. The method includes: generating at least one set of test configuration schemes based on the performance requirements of the module under test and a preset performance scenario; performing performance simulation of the module under test under the preset performance scenario in parallel based on the at least one set of test configuration schemes to trigger at least one target performance event and acquire at least one performance data point through a preset performance monitoring unit; quantifying and analyzing the at least one performance data point to obtain performance analysis results under the preset performance scenario; and updating at least one set of test configuration schemes based on the performance bottleneck when the performance analysis results show a performance bottleneck, thereby determining the optimal configuration parameters of the optimal test configuration scheme based on the updated at least one set of test configuration schemes. This improves performance tuning efficiency, reduces development cycle and labor costs, and ensures that the module under test achieves optimal resource allocation while meeting performance targets.

This invention discloses a method, apparatus, device, and medium for intelligent predictive tuning of JVM based on a large model, relating to the field of artificial intelligence. The method includes: collecting multimodal runtime metric data of a target JVM instance; performing feature engineering on the multimodal runtime metric data to generate standardized feature vectors; inputting the standardized feature vectors into a pre-trained performance prediction model to obtain the predicted probability of a performance degradation event occurring in the target JVM instance within a preset future time window; in response to the predicted probability exceeding a preset probability threshold, generating at least one candidate JVM parameter optimization scheme that satisfies preset objective constraints through a multi-objective constraint optimization algorithm; selecting a target optimization scheme from the at least one candidate JVM parameter optimization schemes, and safely executing the target optimization scheme on the target JVM instance. This invention can significantly improve the accuracy and reliability of JVM performance tuning, effectively enhancing the control effect of JVM performance.

This invention discloses a dynamic chip performance tuning control method and system based on CAVE and reinforcement learning, belonging to the field of integrated circuit testing technology. It aims to solve the problem of low chip tuning efficiency in existing methods. The method includes: measuring the initial actual performance indicators of the chip under test using chip testing hardware, and calculating the performance deviation by combining it with preset target performance indicators; inputting the performance deviation into a pre-trained CVAE model to generate tuning factors; converting the tuning factors into driving instructions to drive tuning execution hardware to perform tuning operations; retesting the actual performance indicators after tuning and calculating new performance deviations, inputting them into a reinforcement learning model to optimize the tuning strategy, until the performance of the chip under test meets a preset tolerance or reaches a preset maximum number of tuning iterations, thus completing the tuning process. This invention achieves dynamic optimization of the tuning strategy, improves modeling stability and tuning accuracy, reduces the number of tuning iterations, requires no manual intervention, adapts to various tuning structures, and improves chip tuning efficiency and yield.

This invention discloses a method, device, and medium for evaluating the ensemble communication performance of large model training. The method includes the following steps: parsing the parallel configuration and model parameters of the target large model, determining the communication operations, communication data volume, and communication process groups to be evaluated, and forming a benchmark test task; executing the benchmark test task and synchronously collecting kernel-level trajectory data from all participating GPU devices; and calculating the effective transmission bandwidth based on the pure communication kernel execution time recorded by all GPU devices in the same communication iteration by analyzing the execution time of the same communication kernel in multiple iterations. This invention solves the problems that existing communication benchmark tests cannot reflect the complex communication patterns of real models and that the measurement results are distorted due to synchronization waiting overhead. In addition, this invention provides key and reliable network parameters for performance simulation, bottleneck analysis, and communication library performance tuning of large model training, with high fidelity and accuracy.