10 results about "Dispatch table" patented technology

This invention discloses a method for reconfigurable modular data plane pipeline assembly and deterministic execution based on XDP. The method includes: generating a Profile configuration file based on the target application scenario, wherein the Profile configuration file describes the module information of the modules to be assembled; obtaining the target information of all modules to be assembled through a loader based on the pre-configured self-describing metadata of the modules, and generating an assembly input list; loading and parsing the Profile configuration file to generate a mapping relationship from stages to module entry points, and writing the mapping relationship into a stage scheduling table; reading the stage scheduling table through the XDP entry scheduler, jumping to the execution entry point of the corresponding module according to the stage scheduling table, and scheduling the execution of the ingress stage chain and the egress stage chain of modules in sequence. This invention abstracts structural changes such as inserting new functional segments, deleting modules, rearranging execution order, and separating ingress and egress processing chains into an assembly problem, thus making it more suitable for building service chains and traffic weaving in physical networks.

The invention discloses a Windows system cross-process malicious behavior detection method, which comprises the following steps of: monitoring the calling of a user mode program on a cross-process memory write-in API (Application Program Interface) through a hook system service scheduling table or a filter drive program of a Windows system, and when detecting that a source process executes memory write-in operation on a target process; when it is monitored that the target process executes the predefined sensitive behavior operation, obtaining a thread call stack address sequence corresponding to the sensitive behavior operation in real time; and comparing the thread call stack address sequence with the injection operation record, and if at least one instruction address in the call stack falls into a memory address range written into the target process by the source process, judging that the sensitive behavior operation forms a malicious behavior initiated by the source process. An injection behavior traceability basis is established by monitoring cross-process memory write-in operation, and accurate behavior traceability of remote code injection attacks is realized for the first time in combination with an address space matching mechanism of a sensitive behavior call stack.

Embodiments of the present application provide a scheduling table restart method and device, a vehicle and a medium. The method comprises: starting the main core to process the scheduling table of at least one slave core; detecting, by the main core, an abnormal condition of the scheduling table of the at least one slave core; and restarting, for a target slave core with an abnormal condition of the scheduling table, the processing of the scheduling table of the target slave core by the main core. The scheduling table is individually specified for each slave core, and the monitoring of the scheduling table of a single slave core is implemented, so that the main core can detect the failure of a single slave core, the individual processing of the scheduling table of a single slave core is implemented, and the functional safety and flexibility of the multi-core system are improved.

The invention relates to the technical field of manufacturing management, in particular to a socket automatic plugging control management system and method, and the system comprises a clamping action recognition module, a control sequence revision module, a signal combination verification module, an abnormal record merging module and a dispatch table content updating module. According to the method, rapid identification and recording of response deviation are realized through numbering and filing of triggering and feedback intervals, association characteristics of abnormal action are verified and judged through feedback combination by adjusting a control instruction sequence, eliminating signal triggering conflicts and time sequence dislocation, and failure point locations and corresponding logics are clarified; according to the method, the repeated fault mode of the device is extracted through abnormal combination, merging, analysis and extraction, the continuous recognition capability of abnormal behaviors is improved, the structural consistency between control logic and task execution is ensured by synchronously revising a scheduling instruction sequence, and the stability and accuracy of a plugging process under a complex working condition and the closed-loop execution capability of scheduling response are enhanced.

The invention discloses a flexible job shop scheduling method oriented to date of delivery constraints. The method is oriented to date of delivery constraints, takes total tardiness and maximum completion time into account, establishes a model comprising process, machine and sequence constraints, and expresses scheduling as Markov decision; constructing a delivery time perception heterogeneous graph composed of process and machine nodes, and explicitly injecting semantics such as urgency degree, residual processing time, queue and predicted idle time in node and edge features by combining three relations of process sequence, process-machine feasibility and same-machine time sequence; tardiness perception graph attention network coding is adopted, a single actor-double commentator structure is matched, and a decision is made in a feasible action set through mask normalization and temperature sampling; the rewards and the event advance are aligned and calculated according to increments, and PPO + GAE is used for stable optimization in the training stage. The method is stable in performance in the aspects of reducing the total tardiness and controlling the maximum completion time, convergence is faster, good generalization is achieved, and the method is suitable for engineering deployment and online application.

The application provides a time partition scheduling method, system, device and medium for a hybrid critical system, and belongs to the technical field of industrial time scheduling. The method comprises the following steps: determining a highest priority task corresponding to a partition in a current time window based on a pre-constructed time partition scheduling table; executing the highest priority task according to an instruction; when the remaining budget time of the highest priority task is less than a preset safety time threshold and the highest priority task is not executed, allocating additional execution time for the highest priority task; by dynamically allocating additional execution time for the highest priority task, the required execution resources can be accurately calculated and supplemented when the remaining budget of the task is insufficient and the execution is not completed, so that the execution interruption, calculation timeout or scheduling exception of the high critical task due to budget depletion is avoided, and the execution certainty and reliability of the system are effectively improved.

The embodiment of the application discloses a code generation method, device, medium and product based on a multi-processor control system; the method comprises the following steps: obtaining model configuration, interface configuration, constraint configuration and verification rules of a to-be-processed control system; generating a task graph according to the model configuration, generating a message flow graph according to the interface configuration, and generating a processor capability table, a bus scheduling table and a synchronization point set according to the constraint configuration; constructing the task graph, the message flow graph, the processor capability table, the bus scheduling table and the synchronization point set into a unified processing object, and the unified processing object is used to represent the associated constraints between tasks, messages, processor resources, bus resources and synchronization points; performing task segmentation, load estimation, mapping solution and interface arrangement based on the unified processing object, and determining a task mapping relationship and an interface scheduling relationship; and generating synchronization code according to the task mapping relationship, the interface scheduling relationship, the synchronization point set and the verification rules.

The invention relates to a task scheduling method and device, equipment, a storage medium and a program product. The method comprises the following steps: respectively starting batch monitoring processes in a plurality of servers in the distributed system, and scanning a batch scheduling table to obtain basic task information of a plurality of periodic tasks; determining a target periodic task according to the last calling time and the execution interval time of each of the plurality of periodic tasks; scanning the batch execution table to obtain an execution record number of the target periodic task in an execution state; and under the condition that the maximum concurrent number of the target periodic tasks is greater than the number of execution records and the current server does not execute the target periodic tasks, executing the target periodic tasks through the current server, adding the execution records in the batch execution table, and updating the last calling time in the batch scheduling table, and the execution duration time reaches the execution interval time. And repeated execution and missing execution of periodic tasks can be avoided.

The invention relates to the field of chip design, in particular to an architecture, a branch execution method and a compiling method of a graphics processor, and the architecture comprises a conditional code register, an active thread mask register, an SIMD (Single Instruction Multiple Data) scheduling table, an SIMD scheduler and an SIMD barrier register. When a branch occurs, the SIMD scheduler can select one branch to execute immediately, and the other branch is stored in the SIMD scheduling table; the SIMD scheduler can suspend the currently executed branch to the SIMD scheduling table at any time, and other branches are recovered from the SIMD scheduling table to continue execution. According to the architecture, branch instructions can be correctly and efficiently executed, and SIMD deadlock is prevented.

The present application relates to GPU chip design technical field, especially in a kind of SIMD divergent thread processing method, equipment and storage medium, it is by setting thread group dispatch table and convergence table to realize the dynamic cutting or merging of thread group.When divergence jump occurs, multiple jump targets are respectively pressed into dispatch table, the direct common post-dominance basic block of jump target is pressed into convergence table, GPU hardware executes from the branch in dispatch table, realizes the dynamic cutting of thread;When uniform jump occurs, according to the contents in jump target and convergence table, the sub-thread group generated by dynamic cutting is re-aggregated together, which allows GPU to flexibly determine which threads are responsible for executing which jump targets, allows the system to dynamically adjust task allocation, improves the parallel execution capability of the system, improves the overall resource utilization.