5 results about "Dispatch table" patented technology

This invention discloses a method for reconfigurable modular data plane pipeline assembly and deterministic execution based on XDP. The method includes: generating a Profile configuration file based on the target application scenario, wherein the Profile configuration file describes the module information of the modules to be assembled; obtaining the target information of all modules to be assembled through a loader based on the pre-configured self-describing metadata of the modules, and generating an assembly input list; loading and parsing the Profile configuration file to generate a mapping relationship from stages to module entry points, and writing the mapping relationship into a stage scheduling table; reading the stage scheduling table through the XDP entry scheduler, jumping to the execution entry point of the corresponding module according to the stage scheduling table, and scheduling the execution of the ingress stage chain and the egress stage chain of modules in sequence. This invention abstracts structural changes such as inserting new functional segments, deleting modules, rearranging execution order, and separating ingress and egress processing chains into an assembly problem, thus making it more suitable for building service chains and traffic weaving in physical networks.

Embodiments of the present application provide a scheduling table restart method and device, a vehicle and a medium. The method comprises: starting the main core to process the scheduling table of at least one slave core; detecting, by the main core, an abnormal condition of the scheduling table of the at least one slave core; and restarting, for a target slave core with an abnormal condition of the scheduling table, the processing of the scheduling table of the target slave core by the main core. The scheduling table is individually specified for each slave core, and the monitoring of the scheduling table of a single slave core is implemented, so that the main core can detect the failure of a single slave core, the individual processing of the scheduling table of a single slave core is implemented, and the functional safety and flexibility of the multi-core system are improved.

The invention discloses a flexible job shop scheduling method oriented to date of delivery constraints. The method is oriented to date of delivery constraints, takes total tardiness and maximum completion time into account, establishes a model comprising process, machine and sequence constraints, and expresses scheduling as Markov decision; constructing a delivery time perception heterogeneous graph composed of process and machine nodes, and explicitly injecting semantics such as urgency degree, residual processing time, queue and predicted idle time in node and edge features by combining three relations of process sequence, process-machine feasibility and same-machine time sequence; tardiness perception graph attention network coding is adopted, a single actor-double commentator structure is matched, and a decision is made in a feasible action set through mask normalization and temperature sampling; the rewards and the event advance are aligned and calculated according to increments, and PPO + GAE is used for stable optimization in the training stage. The method is stable in performance in the aspects of reducing the total tardiness and controlling the maximum completion time, convergence is faster, good generalization is achieved, and the method is suitable for engineering deployment and online application.

The invention relates to a task scheduling method and device, equipment, a storage medium and a program product. The method comprises the following steps: respectively starting batch monitoring processes in a plurality of servers in the distributed system, and scanning a batch scheduling table to obtain basic task information of a plurality of periodic tasks; determining a target periodic task according to the last calling time and the execution interval time of each of the plurality of periodic tasks; scanning the batch execution table to obtain an execution record number of the target periodic task in an execution state; and under the condition that the maximum concurrent number of the target periodic tasks is greater than the number of execution records and the current server does not execute the target periodic tasks, executing the target periodic tasks through the current server, adding the execution records in the batch execution table, and updating the last calling time in the batch scheduling table, and the execution duration time reaches the execution interval time. And repeated execution and missing execution of periodic tasks can be avoided.

The invention relates to the field of chip design, in particular to an architecture, a branch execution method and a compiling method of a graphics processor, and the architecture comprises a conditional code register, an active thread mask register, an SIMD (Single Instruction Multiple Data) scheduling table, an SIMD scheduler and an SIMD barrier register. When a branch occurs, the SIMD scheduler can select one branch to execute immediately, and the other branch is stored in the SIMD scheduling table; the SIMD scheduler can suspend the currently executed branch to the SIMD scheduling table at any time, and other branches are recovered from the SIMD scheduling table to continue execution. According to the architecture, branch instructions can be correctly and efficiently executed, and SIMD deadlock is prevented.