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Branch predictor and method used for operating same

A predictor, branching technology, used in instruments, memory systems, machine execution devices, etc.

Active Publication Date: 2017-02-15
VIA ALLIANCE SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This is challenging because the location of branch instructions within a block is relatively random

Method used

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  • Branch predictor and method used for operating same
  • Branch predictor and method used for operating same
  • Branch predictor and method used for operating same

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Embodiment Construction

[0011] vocabulary

[0012] Hashing two or more entities, such as addresses and branch patterns, refers to performing one or more ANDs on one or more bits of each of two or more entities / Or logical operations to generate a result with fewer bits than the largest of two or more entities. One or more AND / or logic operations may include, but are not limited to: selection of physical pre-positioning; Boolean logic operations including XOR, NAND, AND, OR, NOT, cyclic shift and translation; and Arithmetic operations of, subtraction, multiplication, division, and modulo. To illustrate by example, assume a 100-bit branch history, a 32-bit address, and the result is a 10-bit index. Hashing the address and branch transfer history (that is, hashing the address and the branch transfer history) may include bits [9:0] and bit [19:10] of the branch transfer history and bit [9:] of the branch instruction address. 0] XOR.

[0013] The branch predictor in the embodiment uses the conditional bran...

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PUM

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Abstract

The invention provides a branch predictor and a method for operating the same. The branch predictor contains a block address capable of being used for accessing an instruction byte block of an instruction cache and a first / second byte offset in the instruction byte block. Hash logic performs hash operation on a branch pattern and a first / second address formed by the block address and the first / second byte offset to generate a first / second index. A condition branch predictor receives the first / second index and provides a first / second direction prediction of a first / second condition branch instruction in the instruction byte block in response to the first / second index. In an embodiment, a branch target address cache (BTAC) provides the byte offset, and the first / second direction prediction is statically associated with a first / second target address also provided by the BTAC. Instead, the byte offset is a predetermined value, and the first / second direction prediction is dynamically associated with the first / second target address based on the relative size of the byte offset provided by the BTAC.

Description

Technical field [0001] The present invention relates to the field of processor design, in particular to a branch of multiple conditional branch instruction predictor indexes formed by a hash operation of multiple addresses formed by block addresses and multiple byte offsets and branch instruction history transfers. Predictor. Background technique [0002] In the field of processor design, it is well known that the prediction accuracy requirements of branch instruction predictors are becoming higher and higher. As processor pipeline levels, cache memory access delays, and instruction issuance widths in superscalar architectures increase, this demand becomes even stronger. The branch instruction predictor includes predicting the target address and predicting the direction of the conditional branch instruction, that is, jump or not jump. [0003] Typically, instructions are fetched from the instruction cache in units of relatively large blocks, for example, 16 byte instructions are ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3848G06F9/3806G06F9/3005G06F9/30047G06F12/0875G06F2212/452
Inventor 王小玲杨梦晨陈国华
Owner VIA ALLIANCE SEMICON CO LTD
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