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Block-based branch target address cache

A technology of branch target address and high-speed buffering, which is applied in the field of branch target address cache memory, and can solve the problem of wasting BTAC memory units, etc.

Inactive Publication Date: 2009-05-20
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] Providing separate BTA storage in the BTAC for each instruction in the block wastes memory cells in the BTAC since common instruction groups or blocks are not entirely or even usually composed of branch instructions

Method used

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Examples

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Embodiment Construction

[0016] figure 1 A functional block diagram of processor 10 is depicted. The processor 10 executes instructions in the instruction execution pipeline 12 according to the control logic 11 . In some embodiments, pipeline 12 may be a superscalar design with multiple parallel pipelines. Pipeline 12 includes various registers or latches 16 and one or more arithmetic logic units (ALUs) 18 organized into several pipeline stages. A general purpose register (GPR) file 20 provides registers that make up the top level of the memory hierarchy.

[0017] The pipeline 12 fetches instructions from an instruction cache (I-cache) 22 , where memory address translation and grants are managed by an instruction-side translation lookaside buffer (ITLB) 24 . In parallel, pipeline 12 provides the truncated instruction address to block-based branch target address cache (BTAC) 25 . If the truncated address hits in BTAC 25, BTAC 25 may provide a branch target address (BTA) to I-cache 22 to begin fetch...

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PUM

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Abstract

A Branch Target Address Cache (BTAC) stores a plurality of entries, each BTAC entry associated with a block of two or more instructions that includes at least one branch instruction having been evaluated taken. The BTAC entry includes an indicator of which instruction within the associated block is a taken branch instruction. The BTAC entry also includes the Branch Target Address (BTA) of the taken branch. The block size may, but does not necessarily, correspond to the number of instructions per instruction cache line.

Description

technical field [0001] The present invention relates generally to the field of processors, and in particular, to block-based branch target address caches. Background technique [0002] Microprocessors perform computing tasks in a wide variety of applications. Improving processor performance is a design goal to drive product improvement by enabling faster operation and / or increased functionality through enhanced software. In common embedded applications such as portable electronic devices, saving power and reducing chip size are also important goals in processor design and implementation. [0003] Common modern processors employ a pipelined architecture in which successive instructions each having multiple execution steps are overlapped in execution. This ability to exploit parallelism between instructions in a continuous instruction stream helps improve processor performance. Under ideal conditions and in a processor that has each pipeline stage completed in one cycle fol...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/38
CPCG06F9/3806G06F9/3836G06F9/3858G06F9/38G06F9/30G06F9/46
Inventor 罗德尼·韦恩·史密斯詹姆斯·诺里斯·迪芬德尔夫尔托马斯·安德鲁·萨托里乌斯
Owner QUALCOMM INC
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