In at least one embodiment, a processor includes at least one
execution unit that executes instructions and instruction sequencing logic, coupled to the at least one
execution unit, that fetches instructions from a memory
system for execution by the at least one
execution unit. The instruction sequencing logic including
branch target address prediction circuitry that stores a
branch target address prediction associating a first instruction fetch address with a
branch target address to be used as a second instruction fetch address. The
branch target address prediction circuitry includes
delay logic that, in response to at least a tag portion of a third instruction fetch address matching the first instruction fetch address, delays access to the memory
system utilizing the second instruction fetch address if no
branch target address prediction was made in an immediately previous cycle of operation.