The
semiconductor memory device proposed in the present invention comprises memory cells disposed in the row direction and the column direction, a plurality of first lines by which supply voltages are supplied in order to select memory cells disposed in the row direction among the plurality of cells, a plurality of second lines by which supply voltages are supplied in order to select memory cells disposed in the column direction among the plurality of cells, the
data lines which input and output the data to the selected memory cells, the first power
voltage supply circuit which supplies the predetermined supply voltages to the first lines corresponding with the externally input row address
synchronizing with an act command, and the second power
voltage supply circuit which supplies the predetermined supply voltages to the second lines corresponding with the externally input column address
synchronizing with an act command. It also comprises m pieces of memory banks (m is a natural number larger than 2) which write or read the data into or from the memory cells which are selected one after another in the row or column directions,
data input circuits in which multiple bits of serial data which is larger than 512 bits to be written in the m pieces of memory banks, data output circuits which reads the data from the m pieces of memory banks and output in a form of multiple bits of serial data which is larger than 512 bits, and
data conversion circuits which convert the serial
data input in the
data input circuits to parallel data so that it can be written in each
memory bank or to convert each parallel data read from each
memory bank to serial data so that such data are supplied to the data output circuits.