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Interconnection method among cores of multi-core processor

A multi-core processor and core technology, applied in a variety of digital computer combinations, electrical components, digital transmission systems, etc., can solve the problems of difficult integration, inapplicability to the chip level, and difficulty in implementation, and achieve the effect of convenient implementation.

Inactive Publication Date: 2013-05-15
SUZHOU R&D CENT OF NO 214 RES INST OF CHINA NORTH IND GRP
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Problems solved by technology

Therefore, some existing technologies are not suitable for chip-level interconnection, and some are difficult to realize and not easy to integrate.

Method used

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  • Interconnection method among cores of multi-core processor

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Embodiment 1

[0025] Embodiment one: see attached figure 1 shown.

[0026] A multi-core processor refers to a chip containing two or more "execution cores". Compared with single-core processors, multi-core processors face more challenges when conducting technical research on architecture, such as inter-core communication, memory system, low power consumption, and software and hardware coordination. How to realize mutual cooperation and communication between multi-core cores, to ensure the improvement of processing speed and chip processor performance is the main content of the research on inter-core communication structure, and it is also the focus of academic circles.

[0027] The emergence of NoC (Network on-Chip) has brought continuous development momentum to deep submicron SoC. NoC is a higher-level, larger-scale system on a chip, and a network system on a chip. The core idea of ​​NoC technology is to transplant computer network technology into chip design and completely solve the pr...

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Abstract

The invention relates to an interconnection method among cores of a multi-core processor, and is used for realizing interconnection among inner cores chips of the multi-core processor. The multi-core processor includes m chips and each chip includes n inner cores, wherein m and n are integers. According to the interconnection method among cores of the multi-core processor, a m*n mesh interconnection topological structure based on a RapidIO physical layer protocol is formed among the chips, the interconnection topological structure comprises RapidIO cores corresponding to the chips one-to-one and network interface switches connected with each RapidIO core, and the chips form a serial bus through the RapidIO cores and network interface switches. The interconnection method among cores of the multi-core processor is convenient to realize, easy to be used for integration on chip level and ideal in using effect.

Description

technical field [0001] The invention relates to a method for chip-level interconnection between cores of a multi-core processor. Background technique [0002] With the rapid development of semiconductor process technology, the performance of microprocessors (MCU), digital signal processors (DSP), and programmable gate arrays (FPGA) has been greatly improved, making ultra-large-scale complex operations in practice be more widely applied. But a single processor still cannot meet the growing application requirements. If multiple processors are interconnected into a processor array for multi-core cooperative parallel computing, the data processing capability of the system can be doubled, so the research on multi-core interconnection technology has become an emerging hot issue. [0003] There are many ways to interconnect processors, and different choices can be made in different applications. Parallel bus transfer technology is traditionally used. The structure of this techn...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/16H04L12/861
Inventor 汪健王少轩张磊赵忠惠陈亚宁王宁
Owner SUZHOU R&D CENT OF NO 214 RES INST OF CHINA NORTH IND GRP
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