49 results about "High-Speed Serial Interface" patented technology

The invention relates to a coal flow detection system and a control method thereof, and the system is characterized in that the system specifically comprises the following modules: a weighing detection module, a speed detection module, a temperature compensation module, a data processing module, a communication module, an alarm module, a power management module and a display module; the weighing detection module is connected with a differential input interface of the data processing module through a full-bridge strain circuit; the speed detection module is connected with a timer capture unit of the data processing module through an orthogonal encoder interface; the temperature compensation module is connected with a sensor interface of the data processing module through a digital bus; the data processing module communicates with the communication module and the display module through a high-speed serial interface; the alarm module is connected with the data processing module through an isolated digital output interface. The problem that an existing detection method only depends on single weighing or speed measurement, the actual situation of the coal flow cannot be comprehensively and accurately reflected, and consequently the measurement result error is large is solved.

An output control device of a laser direct writing image comprises a digital micromirror device and a carrying plate, a driving plate is connected with a host and the carrying plate, the host outputs data through a first output port, the driving plate comprises a first input port, a data processor, a display controller, a storage assembly and a second output port, and the first input port is connected with the data processor. The first input port communicates with the first output port, the first input port is connected with the data processor, the data processor is connected with the storage component and the display controller, and the display controller is connected with the second output port; the data processor comprises a first interface unit, a data processing unit and a second interface unit, the input interface of the display controller adopts a high-speed serial interface, and the second output port and the second input port adopt high-speed serial interfaces. The image control data is transmitted at a high speed, so that the transmission rate is greatly improved, and the transmission of ultra-high-rate image data signals is realized.

The invention relates to the technical field of radar interference high-speed transmission, in particular to an SAR (Synthetic Aperture Radar) interference method based on high-speed data transmission, which comprises the following steps of: receiving a radio-frequency signal transmitted by an interfered SAR, performing down-conversion and analog-to-digital conversion on the radio-frequency signal by a radio-frequency receiving front end to obtain an original sampling data stream, and transmitting the original sampling data stream to a programmable logic part through a high-speed serial interface; the method comprises the following steps: extracting pulse description words including pulse arrival time, pulse width, pulse repetition interval and carrier frequency, reconstructing a coherent interference signal baseband waveform in real time according to the pulse description words, and performing digital up-conversion and digital pre-distortion processing on the baseband waveform to generate a target interference intermediate frequency digital signal; and after digital-to-analog conversion and up-conversion are completed, an interference radio frequency signal is radiated. According to the method, data transmission and signal processing delay can be reduced, interference signal coherence is guaranteed, and intermediate frequency signal generation precision and processing real-time performance are improved.

The application discloses a remote online upgrading method and device of a programmable logic device and a medium, wherein a basic firmware area and a use firmware area which do not overlap each other are divided in a FLASH storage space; a host computer cuts a program to be upgraded into fixed frames, and then continuously sends the frames to an FPGA through a high-speed serial interface; the FPGA decodes the frames through an internal GTX high-speed transceiver according to a preset protocol, obtains continuous effective program data, and buffers the data in an on-chip ROM buffer area; a first-erasing-then-writing operation is performed on the FLASH, and the first-erasing-then-writing operation is checked; through double-mirror management of two programs, a timeout trigger is monitored to trigger a rollback to ensure that a basic function of the program can be run; data is transmitted by using the GTX to accelerate the upgrading speed, and the transmission is ensured to be complete through a CRC check and a retransmission mechanism; a pipeline type data transmission is realized through a ping-pong buffer structure; and the upgrading reliability is increased by comparing FLASH writing data.

Aspects of the embodiments are directed to systems, devices, and methods for accessing a storage device as memory. The embodiments include a microprocessor comprising a microprocessor system agent and a field programmable gate array (FPGA). The FPGA includes the FPGA system agent that processes memory access requests received from the microprocessor system agent across a communication link; a memory controller communicatively coupled to the system agent; and a high-speed serial interface linking the system agent with the storage system. The embodiments may also include a storage device connected to the FPGA via the high-speed serial interface.

The application belongs to the technical field of PCIE high-speed serial interface, and discloses a design method and system of a DMA engine module based on FPGA.The system comprises a DMA sending engine module, a DMA receiving engine module and a DMA interrupt module.The application is provided with preset double channels for frequency selection or different mode selection, the channels are in full-duplex mode, the outgoing and incoming are not interfered with each other and are completely controllable.The back transmission comparison self-checking function is added, so that whether the current channel is running normally or not can be judged quickly and conveniently.The DMA sending and receiving state machine transfer method provided by the application can realize more efficient transmission on the premise of using fewer resources.

The utility model relates to the technical field of medical treatment, in particular to a medical endoscope wireless isolation protection device which comprises a transmitting end and a receiving end. The transmitting end comprises an image sensor module, a high-speed serializer and a millimeter wave wireless transmitting module which are connected in sequence; the receiving end comprises a millimeter wave wireless receiving module, a high-speed deserializer, an image processing unit and a display storage module which are connected in sequence; a traditional copper cable is replaced by millimeter wave wireless transmission, high-speed data transmission is achieved, a physical electrical isolation barrier is established, a ground loop and electromagnetic interference of traditional wired transmission are eliminated, meanwhile, a high-speed serial interface is adopted, the number of data lines is reduced during transmission, and signal attenuation is reduced.

The embodiment of the present disclosure relates to a high frame rate DCP image processing system and method. The system comprises an IMB server and a display controller. The IMB server is used to decode a DCP and output video stream data. The display controller is connected to the IMB server through a high-speed serial interface and is used to receive the video stream data and drive an LED display screen. The display controller comprises a security authentication module and an image processing module. The security authentication module is used to establish a secure channel with the IMB server. The image processing module is used to process the received video stream data to generate a signal for driving the LED display screen to display. The high frame rate DCP image processing system and method provided by the embodiment of the present disclosure solve the problems of poor stability caused by complex links and the inability to support high frame rate content caused by insufficient processing capacity in the prior art to some extent.

The invention discloses an energy storage master-slave communication system and method, in the system, a master and a slave both comprise a BMS three-level architecture, and the BMS three-level architecture comprises a BAMS, a BCMU and a BMU which are in communication connection in sequence; the BAMS of the host is respectively connected with the EMS and the PCS, and the BAMS of the host uploads the operation data of the host and the slave to the EMS according to an IEC 60870-5-104 protocol; high-frequency uploading of operation data of the slave and real-time issuing of a control command of the host are completed between the host and the slave through an Aurora high-speed serial bus protocol; the BAMS of the host and the BAMS of the slave both comprise ZYNQ processors and SDRAMs electrically connected with the ZYNQ processors, and the SDRAMs serve as data interaction carrying carriers and are used for caching various data in a partitioned mode. According to the invention, point-to-point high-frequency communication between the master and the slave is realized by relying on the ZYNQ processor on the BAMS of the master and the slave and using an Aurora high-speed serial interface protocol, so that state evaluation, health prediction, balance control and power distribution of the whole station can be completed.

The present application relates to radar interference high-speed transmission technical field, specifically for SAR radar interference method based on high-speed data transmission, including: receiving the radio frequency signal of the interfered synthetic aperture radar transmission, the original sampling data stream is obtained through the down conversion and analog-digital conversion of radio frequency receiving front end, through high-speed serial interface transmission to programmable logic part, the pulse description word containing pulse arrival time, pulse width, pulse repetition interval, carrier frequency is extracted, the baseband waveform of coherent interference signal is reconstructed in real time according to pulse description word, the target interference intermediate frequency digital signal is generated by carrying out digital up conversion and digital predistortion processing to baseband waveform, and the interference radio frequency signal is radiated after completing digital-analog conversion and up conversion through high-speed serial interface transmission to radio frequency transmitting front end.This method can reduce data transmission and signal processing delay, guarantee the coherence of interference signal, improve the generation accuracy and processing real-time performance of intermediate frequency signal.

The invention provides a driving method, a driving system and a display device. The driving method comprises the following steps: in a display period, controlling a display driving module to receive display data from a system-on-chip through a high-speed serial interface, and driving sub-pixels in a display panel to work by using the display data; and in the blanking period, the touch sensing module is controlled to receive original touch data from the display panel, and the touch data obtained after the original touch data is processed is sent to the system-on-chip through the high-speed serial interface. Specifically, the display data and the touch data are transmitted between the integrated chip and the system-on-chip through the high-speed serial interface by performing time division multiplexing on the high-speed serial interface in the display period and the blanking period, so that the number of system pins can be effectively reduced, and the cost of the connector can be reduced. In addition, the original touch data / touch data is transmitted by utilizing the blanking period, so that the interference on normal display can be avoided, and the system stability is improved.

The invention discloses a satellite communication processing load device, and belongs to the field of satellite communication and aerospace engineering. The device comprises a main backup routing exchange unit, a load control unit, a plurality of feed processing units and a plurality of user processing units. Wherein the route switching unit is connected with all the processing units through high-speed serial interfaces to form a double-star type service network; and the load control unit is connected with all the units through medium-speed interfaces to form an annular control network. According to the invention, each unit is realized through the FPGA, and the health state of the bus is monitored in real time by using the signal detection module. When the main route switching unit breaks down or receives a switching instruction, the load control unit can automatically coordinate to complete a series of operations such as power-on of the backup unit, service and control link reconstruction and the like, rapid and autonomous switching of a main bus and a backup bus of the system is achieved, and the reliability and on-orbit autonomous maintenance capacity of the satellite communication system are remarkably improved.

The utility model relates to a kind of 100G optical module, including main control circuit;Wherein, main control circuit is connected with driver and receiver array, driver is connected with fiber transmitter, and receiver array is connected with fiber receiver;Connector is detachably electrically connected with external switch for electric signal communication, main control circuit and switch carry out communication control driver and the work of receiver array, driver is according to the electric signal of switch output drive fiber transmitter transmit fiber signal, and receiver array receives the electric signal sent by fiber receiver and is output to switch after amplification;Fiber transmitter is used to convert electric signal into fiber signal, and fiber receiver is used to convert fiber signal into electric signal;Wherein, fiber transmitter and fiber receiver all support high-speed serial interface protocol communication, greatly improve communication rate;So as to realize photoelectric conversion, and be equipped with main control circuit and temperature control circuit, greatly improve the stability and working performance of product, improve user experience.

A first device communicating with a second device through a high-speed serial interface includes an interface controller configured to recover data received via the high-speed serial interface and a component configured to perform a selected operation based on the recovered data, the interface controller including a recovered clock domain circuit configured to operate based on a recovered clock corresponding to a data transmission rate of the high-speed serial interface and a local clock domain circuit configured to operate based on a local clock having a frequency adaptively controlled based on a frequency of the recovered clock.

The application discloses a kind of multi-channel high-speed time delay synchronous acquisition device and method, belong to communication signal processing technical field.The device includes reference source, timer, high-speed acquisition unit and FPGA chip;Reference source provides phase-locked clock, timer generates sampling start pulse and sends to the FPGA chip, high-speed acquisition unit is acquired under the control of the SYNC signal sent by the FPGA chip Multi-channel signal, and acquisition data is sent to the FPGA chip by high-speed serial interface;FPGA chip receives the acquisition data sent by the high-speed acquisition unit and carries out time delay compensation, realizes multi-channel time delay synchronization.The application does not need to be strictly phase alignment with the SYNC signal of multiple pieces of ADC sampling clock, reduces the difficulty of PCB design, is suitable for mass production.

The invention belongs to the technical field of signal processing, and discloses an FPGA software intermediate data recording method based on embedded selection words. The intermediate data recording method is suitable for signal processing FPGA software design with high-speed serial input and output and DDR storage, selection words are embedded in input data, and recording of intermediate data in the FPGA software can be achieved without adding an additional input interface. In the operation process of the FPGA, a user can select output data of one module in the FPGA software as record data each time, store the record data in the DDR or output the record data from the high-speed serial interface, and subsequently read the record data in the DDR through the CPU for analysis, or connect a recorder with the high-speed serial interface to store the record data for analysis.

The embodiments of the present application relate to the field of chip technology, and provide a high-speed serial interface and a data transmission method, so as to reduce the power consumption of the physical layer circuit of the high-speed serial interface when service data is not being transmitted. The high-speed serial interface includes a physical layer circuit of a transmitting end, a monitor, a clock gating circuit, a control bit stream generating circuit, and a random bit stream generating circuit, and further, the monitor is configured to indicate to the clock gating circuit to stop sending a clock signal to a partial module in the physical layer circuit of the transmitting end when service data is not being transmitted. The control bit stream generating circuit transmits a first control bit stream through the serializer / deserializer to indicate that the transmitting end has turned off the partial module in the physical layer circuit of the transmitting end, or to indicate that the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or to indicate to the receiving end to turn off the partial module in the physical layer circuit of the receiving end. The random bit stream generating circuit transmits a random bit stream. The embodiments of the present application are used in the process of reducing the power consumption of the physical layer circuit.

A data transmission chip and an electronic device are provided, and belong to the field of electronic technologies. A low-speed interface of the data transmission chip is configured to receive a plurality of channels of first signals, and a high-speed serial interface of the data transmission chip is configured to serially transmit the plurality of channels of first signals to another data transmission chip in a form of a data frame.

This invention discloses a multimodal data transmission system and method for a pantograph monitoring system, including a roof-mounted detection module, a transmission link, and an in-vehicle host computer. The roof-mounted detection module integrates a one-dimensional signal detection unit, a two-dimensional signal detection unit, a main control unit, and a buffer unit. The one-dimensional and two-dimensional signal detection units are respectively connected to the data input terminal of the main control unit through signal interfaces. The buffer unit is integrated with or electrically connected to the main control unit. The data output terminal of the main control unit is connected to the roof of the transmission link through a high-speed serial interface. The in-vehicle end of the transmission link is connected to the in-vehicle host computer. The in-vehicle host computer periodically sends a synchronization trigger signal through the transmission link to trigger the data packaging and uploading of the roof-mounted detection module. Time reconstruction and multimodal data alignment are performed based on the returned data. This invention improves the alignment accuracy of one-dimensional waveforms and two-dimensional images on the time axis from milliseconds to microseconds, ensuring the absolute accuracy of arcing event location.

The application discloses a kind of wideband high-speed digital frequency hopping system and method based on direct frequency generation.The system includes FPGA, digital-analog converter and clock chip, wherein the FPGA has differential high-speed serial interface, is configured as JESD204B high-speed interface;The digital-analog converter captures entire spectrum at a time, built-in DDC digital frequency conversion and FIR filter, support up to 6GHz radio frequency frequency direct generation;The clock chip generates two-way 256MHz differential LVDS clock, and the working clock of FPGA and digital-analog converter is all used 256MHz clock.The method includes baseband IQ signal generation, baseband IQ signal interpolation filtering, odd-even sequence splitting, odd-even sequence digital frequency conversion, odd-even sequence merging sending, digital up-conversion and radio frequency output these steps.The application has high reliability, low cost, small volume, low power consumption, and has excellent anti-interference performance.

The application belongs to the technical field of integrated circuits, and discloses a 5Gbps low-voltage differential signal driving circuit for a high-speed serial interface. The circuit is suitable for a 1.8V power supply voltage, and the output voltage swings 350mV on a 0.9V reference voltage. The whole circuit is simulated after being completed by using a 40nm process on a platform Cadence Spectre. A high-speed level shifter for voltage domain conversion is designed, so that the high-speed transmission of the LVDS is ensured.

The invention discloses a simulation debugging system and method and a computer readable storage medium, the simulation debugging system comprises a host and a hardware simulation acceleration platform, the host comprises a first high-speed serial interface subsystem, and the hardware simulation acceleration platform comprises a programmable logic device; the programmable logic device is used for receiving debugging information forwarded by a debugging and testing subsystem in the tested equipment; performing format conversion on each piece of debugging information to obtain each piece of debugging information after format conversion; coding each piece of debugging information after format conversion to obtain each piece of coded debugging information; each piece of coded debugging information is returned to the debugging and testing subsystem; the host is used for receiving each piece of coded debugging information sent by the debugging and testing subsystem through the second high-speed serial interface subsystem through the first high-speed serial interface subsystem; and decoding each piece of coded debugging information, and carrying out simulation debugging according to the obtained decoded debugging information. According to the method, the simulation debugging time is shortened, debugging information transmission of multiple devices is supported, and computing resources are saved.

The invention relates to the technical field of high-speed digital-to-analog conversion, and discloses a pulse width error calibration method of an ultra-high-speed digital-to-analog converter. According to the method, in a time interleaving architecture of a multi-sub DAC, high-precision compensation of a pulse width error is realized through target sampling, time-sharing point sampling, correlation analysis and a least mean square (LMS) adaptive algorithm. The method innovatively introduces a'advanced counting point 'strategy, periodically predicts a sampling position by using a test signal, avoids large-scale register storage, and realizes data acquisition with low hardware overhead. An ideal value and a channel reflection effect are eliminated through difference of adjacent sampling points, a pulse width error control word is accurately updated in combination with a bandwidth compensation factor, and the pulse width error control word only acts on a corresponding sub-DAC. The scheme reduces the pulse width error from about 1ps to about 50fs in Matlab simulation, has the advantages of high precision, low power consumption, strong stability and small area occupation, and is suitable for high-speed serial interface chips and coherent / incoherent optical chips.

The present disclosure provides an exception positioning system, method, electronic device and storage medium, and relates to the field of server exception detection.The system comprises a baseboard management controller having a first high-speed serial interface, a plurality of graphic processors, and a controller device.The graphic processors each have a joint test action group interface and a serial interface.The controller device comprises a high-speed serial switching module, a first conversion module, a second conversion module, a serial interface module and a joint test action group interface module.The baseboard management controller acquires register information and state information of the serial interface in parallel through the first high-speed serial signal line to perform exception positioning.The present disclosure can acquire joint test action group and state information of the plurality of graphic processors in parallel, and greatly improves the efficiency of exception positioning.

The invention provides a vehicle-mounted data acquisition gateway device, which comprises a programmable logic array, a multi-path CAN (Controller Area Network) equipment interface circuit, a multi-path Ethernet interface circuit, a solid-state storage circuit and a high-speed serial interface circuit, the solid-state storage circuit, the multi-path CAN equipment interface circuit, the multi-path Ethernet interface circuit and the high-speed serial interface circuit are respectively connected with the programmable logic array, each path of CAN equipment interface circuit is correspondingly connected with each path of CANBUS bus system, and the multi-path Ethernet interface circuit is respectively connected with the host terminal and the network terminal. The high-speed serial interface circuit is connected with the mobile storage device; and the programmable logic array is used for controlling the driving of each interface circuit and realizing the transceiving management and storage of data under the condition of no operating system, and sending a timing pulse frame to the host terminal so as to enable the host terminal to carry out state monitoring on the vehicle-mounted data acquisition gateway device.

This application relates to a method for adjusting the output impedance of a radio frequency (RF) remote unit device. The method includes: with the RF remote unit device operating at nominal full power, determining the expected reflected power based on the VSWR (Standing Wave Ratio) of the mismatched load connected to the output of the RF remote unit device and the rated transmit power; converting the power amplifier reflected signal of the RF remote unit device into a digital signal based on the feedback channel of the attenuator, the RF reflection link, and the radio transceiver; acquiring the digital signal through a field-programmable gate array (FPGA) using the high-speed serial interface of the RF remote unit device; determining the initial actual reflected power based on the digital signal using the FPGA; and adjusting the capacitor control voltage of a voltage-controlled capacitor according to the expected reflected power and the initial actual reflected power, thereby adjusting the output impedance of the RF remote unit device. This solution saves on manufacturing costs for mass production of the equipment and improves equipment stability.

This invention discloses a dual-processor EtherCAT motion control integrated machine and control method, belonging to the field of industrial automation control. The integrated machine includes a first processor and a second processor interconnected via a high-speed serial interface. The first processor executes user logic and interpolation algorithms, and manages local I / O and pulse output. The second processor is dedicated to running the EtherCAT master protocol and managing bus slaves. The first processor issues commands to the second processor regarding EtherCAT axes and extended I / O via the high-speed interface and receives status feedback, achieving unified control of pulse axes, EtherCAT axes, and local and remote I / O. The method includes steps such as initialization, command parsing, dual-core collaborative processing, and status synchronization. This invention solves the problems of functional dispersion, insufficient real-time performance, and poor compatibility through heterogeneous division of labor and high-speed interconnection, achieving highly integrated, real-time-efficient, and flexibly expandable motion control.

A multiphasic traction elevator control system is disclosed, incorporating an advanced S-curve motion profile to optimize ride comfort, energy efficiency, and mechanical durability. The system features a central controller, a motor room board, and car and hall panel controllers communicating via a high-speed serial interface. A motion planning module dynamically calculates acceleration, cruising, and deceleration phases, adapting real-time speed adjustments to enhance efficiency. The system supports multiple operational profiles, including normal, short-distance, emergency power, and inspection modes, each with optimized jerk and velocity constraints. A mid-flight destination adjustment algorithm modifies motion profiles without abrupt speed changes. A stop rejection mechanism prevents unsafe or inefficient stops. Real-time speed monitoring in the inspection profile ensures precise velocity control. A precision floor leveling algorithm enhances stopping accuracy. The invention provides a high-speed, intelligent, and adaptive elevator control system, reducing mechanical wear while ensuring passenger safety and comfort.

This invention discloses a satellite communication processing payload device, belonging to the fields of satellite communication and aerospace engineering. The device includes a primary and backup routing and switching unit and a payload control unit, as well as multiple power supply processing units and user processing units. The routing and switching unit connects to all processing units via a high-speed serial interface, forming a dual-satellite service network; the payload control unit connects to all units via a medium-speed interface, forming a ring control network. This invention implements each unit using an FPGA and utilizes a signal detection module to monitor the bus health status in real time. When the primary routing and switching unit fails or receives a switching command, the payload control unit can automatically coordinate a series of operations, including powering on the backup unit and rebuilding the service and control links, achieving rapid and autonomous switching of the system's primary and backup buses, significantly improving the reliability and on-orbit autonomous maintenance capability of the satellite communication system.

The invention relates to the technical field of integrated circuit design and communication, in particular to a SerDes core grain design method, which comprises the following steps: designing interfaces of SerDes core grains, including a high-speed serial interface, a parallel interface and a configuration interface; high-speed data transmission with an external device or equipment is realized through the high-speed serial interface; butt joint of the SerDes core particles and chip / system internal core particles is realized through the parallel interface; dynamically adjusting parameters of the SerDes core particles through the configuration interface; a SerDes core particle is designed, and the SerDes core particle comprises a physical medium adaptation layer (PMA), a control unit and a clock module. A configurable parallel interface, clock data synchronous transmission and a modular architecture are adopted, the communication efficiency and flexibility between chips and systems are improved, the development period is shortened, and the cost is reduced.