30 results about "High-Speed Serial Interface" patented technology

The invention relates to the technical field of radar interference high-speed transmission, in particular to an SAR (Synthetic Aperture Radar) interference method based on high-speed data transmission, which comprises the following steps of: receiving a radio-frequency signal transmitted by an interfered SAR, performing down-conversion and analog-to-digital conversion on the radio-frequency signal by a radio-frequency receiving front end to obtain an original sampling data stream, and transmitting the original sampling data stream to a programmable logic part through a high-speed serial interface; the method comprises the following steps: extracting pulse description words including pulse arrival time, pulse width, pulse repetition interval and carrier frequency, reconstructing a coherent interference signal baseband waveform in real time according to the pulse description words, and performing digital up-conversion and digital pre-distortion processing on the baseband waveform to generate a target interference intermediate frequency digital signal; and after digital-to-analog conversion and up-conversion are completed, an interference radio frequency signal is radiated. According to the method, data transmission and signal processing delay can be reduced, interference signal coherence is guaranteed, and intermediate frequency signal generation precision and processing real-time performance are improved.

The application discloses a remote online upgrading method and device of a programmable logic device and a medium, wherein a basic firmware area and a use firmware area which do not overlap each other are divided in a FLASH storage space; a host computer cuts a program to be upgraded into fixed frames, and then continuously sends the frames to an FPGA through a high-speed serial interface; the FPGA decodes the frames through an internal GTX high-speed transceiver according to a preset protocol, obtains continuous effective program data, and buffers the data in an on-chip ROM buffer area; a first-erasing-then-writing operation is performed on the FLASH, and the first-erasing-then-writing operation is checked; through double-mirror management of two programs, a timeout trigger is monitored to trigger a rollback to ensure that a basic function of the program can be run; data is transmitted by using the GTX to accelerate the upgrading speed, and the transmission is ensured to be complete through a CRC check and a retransmission mechanism; a pipeline type data transmission is realized through a ping-pong buffer structure; and the upgrading reliability is increased by comparing FLASH writing data.

The utility model relates to the technical field of medical treatment, in particular to a medical endoscope wireless isolation protection device which comprises a transmitting end and a receiving end. The transmitting end comprises an image sensor module, a high-speed serializer and a millimeter wave wireless transmitting module which are connected in sequence; the receiving end comprises a millimeter wave wireless receiving module, a high-speed deserializer, an image processing unit and a display storage module which are connected in sequence; a traditional copper cable is replaced by millimeter wave wireless transmission, high-speed data transmission is achieved, a physical electrical isolation barrier is established, a ground loop and electromagnetic interference of traditional wired transmission are eliminated, meanwhile, a high-speed serial interface is adopted, the number of data lines is reduced during transmission, and signal attenuation is reduced.

The embodiment of the present disclosure relates to a high frame rate DCP image processing system and method. The system comprises an IMB server and a display controller. The IMB server is used to decode a DCP and output video stream data. The display controller is connected to the IMB server through a high-speed serial interface and is used to receive the video stream data and drive an LED display screen. The display controller comprises a security authentication module and an image processing module. The security authentication module is used to establish a secure channel with the IMB server. The image processing module is used to process the received video stream data to generate a signal for driving the LED display screen to display. The high frame rate DCP image processing system and method provided by the embodiment of the present disclosure solve the problems of poor stability caused by complex links and the inability to support high frame rate content caused by insufficient processing capacity in the prior art to some extent.

The present application relates to radar interference high-speed transmission technical field, specifically for SAR radar interference method based on high-speed data transmission, including: receiving the radio frequency signal of the interfered synthetic aperture radar transmission, the original sampling data stream is obtained through the down conversion and analog-digital conversion of radio frequency receiving front end, through high-speed serial interface transmission to programmable logic part, the pulse description word containing pulse arrival time, pulse width, pulse repetition interval, carrier frequency is extracted, the baseband waveform of coherent interference signal is reconstructed in real time according to pulse description word, the target interference intermediate frequency digital signal is generated by carrying out digital up conversion and digital predistortion processing to baseband waveform, and the interference radio frequency signal is radiated after completing digital-analog conversion and up conversion through high-speed serial interface transmission to radio frequency transmitting front end.This method can reduce data transmission and signal processing delay, guarantee the coherence of interference signal, improve the generation accuracy and processing real-time performance of intermediate frequency signal.

The invention provides a driving method, a driving system and a display device. The driving method comprises the following steps: in a display period, controlling a display driving module to receive display data from a system-on-chip through a high-speed serial interface, and driving sub-pixels in a display panel to work by using the display data; and in the blanking period, the touch sensing module is controlled to receive original touch data from the display panel, and the touch data obtained after the original touch data is processed is sent to the system-on-chip through the high-speed serial interface. Specifically, the display data and the touch data are transmitted between the integrated chip and the system-on-chip through the high-speed serial interface by performing time division multiplexing on the high-speed serial interface in the display period and the blanking period, so that the number of system pins can be effectively reduced, and the cost of the connector can be reduced. In addition, the original touch data / touch data is transmitted by utilizing the blanking period, so that the interference on normal display can be avoided, and the system stability is improved.

The invention discloses a satellite communication processing load device, and belongs to the field of satellite communication and aerospace engineering. The device comprises a main backup routing exchange unit, a load control unit, a plurality of feed processing units and a plurality of user processing units. Wherein the route switching unit is connected with all the processing units through high-speed serial interfaces to form a double-star type service network; and the load control unit is connected with all the units through medium-speed interfaces to form an annular control network. According to the invention, each unit is realized through the FPGA, and the health state of the bus is monitored in real time by using the signal detection module. When the main route switching unit breaks down or receives a switching instruction, the load control unit can automatically coordinate to complete a series of operations such as power-on of the backup unit, service and control link reconstruction and the like, rapid and autonomous switching of a main bus and a backup bus of the system is achieved, and the reliability and on-orbit autonomous maintenance capacity of the satellite communication system are remarkably improved.

A first device communicating with a second device through a high-speed serial interface includes an interface controller configured to recover data received via the high-speed serial interface and a component configured to perform a selected operation based on the recovered data, the interface controller including a recovered clock domain circuit configured to operate based on a recovered clock corresponding to a data transmission rate of the high-speed serial interface and a local clock domain circuit configured to operate based on a local clock having a frequency adaptively controlled based on a frequency of the recovered clock.

The application discloses a kind of multi-channel high-speed time delay synchronous acquisition device and method, belong to communication signal processing technical field.The device includes reference source, timer, high-speed acquisition unit and FPGA chip;Reference source provides phase-locked clock, timer generates sampling start pulse and sends to the FPGA chip, high-speed acquisition unit is acquired under the control of the SYNC signal sent by the FPGA chip Multi-channel signal, and acquisition data is sent to the FPGA chip by high-speed serial interface;FPGA chip receives the acquisition data sent by the high-speed acquisition unit and carries out time delay compensation, realizes multi-channel time delay synchronization.The application does not need to be strictly phase alignment with the SYNC signal of multiple pieces of ADC sampling clock, reduces the difficulty of PCB design, is suitable for mass production.

The invention belongs to the technical field of signal processing, and discloses an FPGA software intermediate data recording method based on embedded selection words. The intermediate data recording method is suitable for signal processing FPGA software design with high-speed serial input and output and DDR storage, selection words are embedded in input data, and recording of intermediate data in the FPGA software can be achieved without adding an additional input interface. In the operation process of the FPGA, a user can select output data of one module in the FPGA software as record data each time, store the record data in the DDR or output the record data from the high-speed serial interface, and subsequently read the record data in the DDR through the CPU for analysis, or connect a recorder with the high-speed serial interface to store the record data for analysis.

The embodiments of the present application relate to the field of chip technology, and provide a high-speed serial interface and a data transmission method, so as to reduce the power consumption of the physical layer circuit of the high-speed serial interface when service data is not being transmitted. The high-speed serial interface includes a physical layer circuit of a transmitting end, a monitor, a clock gating circuit, a control bit stream generating circuit, and a random bit stream generating circuit, and further, the monitor is configured to indicate to the clock gating circuit to stop sending a clock signal to a partial module in the physical layer circuit of the transmitting end when service data is not being transmitted. The control bit stream generating circuit transmits a first control bit stream through the serializer / deserializer to indicate that the transmitting end has turned off the partial module in the physical layer circuit of the transmitting end, or to indicate that the transmitting end turns off the partial module in the physical layer circuit of the transmitting end, or to indicate to the receiving end to turn off the partial module in the physical layer circuit of the receiving end. The random bit stream generating circuit transmits a random bit stream. The embodiments of the present application are used in the process of reducing the power consumption of the physical layer circuit.

A data transmission chip and an electronic device are provided, and belong to the field of electronic technologies. A low-speed interface of the data transmission chip is configured to receive a plurality of channels of first signals, and a high-speed serial interface of the data transmission chip is configured to serially transmit the plurality of channels of first signals to another data transmission chip in a form of a data frame.

This invention discloses a multimodal data transmission system and method for a pantograph monitoring system, including a roof-mounted detection module, a transmission link, and an in-vehicle host computer. The roof-mounted detection module integrates a one-dimensional signal detection unit, a two-dimensional signal detection unit, a main control unit, and a buffer unit. The one-dimensional and two-dimensional signal detection units are respectively connected to the data input terminal of the main control unit through signal interfaces. The buffer unit is integrated with or electrically connected to the main control unit. The data output terminal of the main control unit is connected to the roof of the transmission link through a high-speed serial interface. The in-vehicle end of the transmission link is connected to the in-vehicle host computer. The in-vehicle host computer periodically sends a synchronization trigger signal through the transmission link to trigger the data packaging and uploading of the roof-mounted detection module. Time reconstruction and multimodal data alignment are performed based on the returned data. This invention improves the alignment accuracy of one-dimensional waveforms and two-dimensional images on the time axis from milliseconds to microseconds, ensuring the absolute accuracy of arcing event location.

The application discloses a kind of wideband high-speed digital frequency hopping system and method based on direct frequency generation.The system includes FPGA, digital-analog converter and clock chip, wherein the FPGA has differential high-speed serial interface, is configured as JESD204B high-speed interface;The digital-analog converter captures entire spectrum at a time, built-in DDC digital frequency conversion and FIR filter, support up to 6GHz radio frequency frequency direct generation;The clock chip generates two-way 256MHz differential LVDS clock, and the working clock of FPGA and digital-analog converter is all used 256MHz clock.The method includes baseband IQ signal generation, baseband IQ signal interpolation filtering, odd-even sequence splitting, odd-even sequence digital frequency conversion, odd-even sequence merging sending, digital up-conversion and radio frequency output these steps.The application has high reliability, low cost, small volume, low power consumption, and has excellent anti-interference performance.

The application belongs to the technical field of integrated circuits, and discloses a 5Gbps low-voltage differential signal driving circuit for a high-speed serial interface. The circuit is suitable for a 1.8V power supply voltage, and the output voltage swings 350mV on a 0.9V reference voltage. The whole circuit is simulated after being completed by using a 40nm process on a platform Cadence Spectre. A high-speed level shifter for voltage domain conversion is designed, so that the high-speed transmission of the LVDS is ensured.

This application relates to a method for adjusting the output impedance of a radio frequency (RF) remote unit device. The method includes: with the RF remote unit device operating at nominal full power, determining the expected reflected power based on the VSWR (Standing Wave Ratio) of the mismatched load connected to the output of the RF remote unit device and the rated transmit power; converting the power amplifier reflected signal of the RF remote unit device into a digital signal based on the feedback channel of the attenuator, the RF reflection link, and the radio transceiver; acquiring the digital signal through a field-programmable gate array (FPGA) using the high-speed serial interface of the RF remote unit device; determining the initial actual reflected power based on the digital signal using the FPGA; and adjusting the capacitor control voltage of a voltage-controlled capacitor according to the expected reflected power and the initial actual reflected power, thereby adjusting the output impedance of the RF remote unit device. This solution saves on manufacturing costs for mass production of the equipment and improves equipment stability.

This invention discloses a dual-processor EtherCAT motion control integrated machine and control method, belonging to the field of industrial automation control. The integrated machine includes a first processor and a second processor interconnected via a high-speed serial interface. The first processor executes user logic and interpolation algorithms, and manages local I / O and pulse output. The second processor is dedicated to running the EtherCAT master protocol and managing bus slaves. The first processor issues commands to the second processor regarding EtherCAT axes and extended I / O via the high-speed interface and receives status feedback, achieving unified control of pulse axes, EtherCAT axes, and local and remote I / O. The method includes steps such as initialization, command parsing, dual-core collaborative processing, and status synchronization. This invention solves the problems of functional dispersion, insufficient real-time performance, and poor compatibility through heterogeneous division of labor and high-speed interconnection, achieving highly integrated, real-time-efficient, and flexibly expandable motion control.

A multiphasic traction elevator control system is disclosed, incorporating an advanced S-curve motion profile to optimize ride comfort, energy efficiency, and mechanical durability. The system features a central controller, a motor room board, and car and hall panel controllers communicating via a high-speed serial interface. A motion planning module dynamically calculates acceleration, cruising, and deceleration phases, adapting real-time speed adjustments to enhance efficiency. The system supports multiple operational profiles, including normal, short-distance, emergency power, and inspection modes, each with optimized jerk and velocity constraints. A mid-flight destination adjustment algorithm modifies motion profiles without abrupt speed changes. A stop rejection mechanism prevents unsafe or inefficient stops. Real-time speed monitoring in the inspection profile ensures precise velocity control. A precision floor leveling algorithm enhances stopping accuracy. The invention provides a high-speed, intelligent, and adaptive elevator control system, reducing mechanical wear while ensuring passenger safety and comfort.

This invention discloses a satellite communication processing payload device, belonging to the fields of satellite communication and aerospace engineering. The device includes a primary and backup routing and switching unit and a payload control unit, as well as multiple power supply processing units and user processing units. The routing and switching unit connects to all processing units via a high-speed serial interface, forming a dual-satellite service network; the payload control unit connects to all units via a medium-speed interface, forming a ring control network. This invention implements each unit using an FPGA and utilizes a signal detection module to monitor the bus health status in real time. When the primary routing and switching unit fails or receives a switching command, the payload control unit can automatically coordinate a series of operations, including powering on the backup unit and rebuilding the service and control links, achieving rapid and autonomous switching of the system's primary and backup buses, significantly improving the reliability and on-orbit autonomous maintenance capability of the satellite communication system.

The invention relates to the technical field of integrated circuits and provides a high-speed serial interface physical IP verification platform, method and device and a medium. The invention provides a unified design and verification platform which supports coexistence and fusion of multiple protocol types and can be used for design and verification of a multi-protocol physical layer intellectual property core, and is based on a modular, parameterized and multi-protocol harmonious coexistence design idea and a top-layer architecture circuit design method. In project development, the circuit design and verification labor cost of various different protocol types can be effectively reduced, the function and performance verification period of the physical layer intellectual property core is remarkably shortened, the full-stack and full-field research and development efficiency of architecture design, circuit development and function / performance full-amount verification for different protocol types is remarkably improved, and the development efficiency of the physical layer intellectual property core is remarkably improved. The multiplexing degree of design and verification platforms between different protocols is improved, and an excellent normal form of unified design and verification with extremely high platform level is provided.

The invention relates to the technical field of high-speed communication and signal processing, and discloses a self-adaptive equalizer signal compensation method and system for a high-speed serial interface, and the method comprises the steps: obtaining the real-time sampling data of the interface, determining an equalization coefficient through dynamic self-adaptive filtering, and extracting the features of a monitoring signal; calculating environmental interference intensity according to the characteristics, and if the environmental interference intensity exceeds the standard, triggering genetic evolution to obtain optimized parameters; constructing a constraint matrix to correct parameter deviation, generating balance configuration and mapping the balance configuration to a virtual link for stability simulation; if simulation jitter exceeds the standard, historical non-convergent individuals are called for backtracking and re-optimization; real-time error iteration and smoothing processing are carried out based on the environment reference, and a final compensation strategy is determined; and finally, driving a physical link to construct a verification digital eye pattern and counting error codes to obtain communication quality data. The method can solve the problem of low signal compensation precision in the prior art.

The invention discloses a high-speed area-array camera system based on 40G network transmission and an image acquisition and transmission method, and belongs to the technical field of high-speed image acquisition and transmission. The technical problems that a traditional high-speed area-array camera is insufficient in bandwidth, high in system delay and low in multi-camera synchronization precision in a high-resolution and high-frame-rate scene are solved, and the technical scheme is characterized in that the high-speed area-array camera comprises a sensor array, a front-end FPGA module, a rear-end FPGA module and a software deployment end; the sensor array comprises a plurality of groups of image sensors used for collecting original image data and outputting differential data signals, the front-end FPGA module receives the differential data signals, performs image preprocessing and then outputs the signals through a high-speed serial interface, and the rear-end FPGA module performs data analysis and image recombination and then outputs the signals through a QSFP + interface in an optical fiber mode. And the software deployment end receives the image data in parallel through the multi-path optical fiber interface and performs synchronous fusion processing.

An intelligent unmanned ship real-time state monitoring and situation prediction system is characterized in that a multi-source sensor module is connected to an embedded main control unit through a CAN bus or an Ethernet interface; the embedded main control unit is connected with an edge calculation module through a high-speed serial interface; the data processing module is used for packaging original sensing data and transmitting the data to the edge calculation module for local preprocessing, the edge calculation module is connected with the communication relay module through a 4G / 5G or satellite communication link, and state data after compression and feature extraction are uploaded to the shore-based situation fusion center. According to the invention, through three-dimensional deployment and tight coupling fusion of a multi-source heterogeneous sensor, an all-medium environment cognitive ability covering an air, water surface and underwater three-dimensional space is constructed, an inertial measurement unit and a global navigation satellite system receiver adopt hardware-level tight coupling packaging, and microsecond-level timestamp alignment and original observation value synchronization are realized by an onboard FPGA (Field Programmable Gate Array). The continuity and robustness of dynamic high-precision positioning are improved, and the accumulative error of the pure inertial navigation system is effectively inhibited.

An isolation high-speed serial interface integrated circuit supporting a switchable protocol comprises an FPGA module, a digital isolation module, a level conversion module, an analog switch module and an external communication interface, and the FPGA module is used for processing UART signals, input and output of synchronous clock signals, signal enabling control and switching configuration of RS232, RS485 and RS422 modes; the digital isolation module isolates an interface signal from an FPGA port signal through two groups of mutually isolated power supplies; the level conversion module is used for converting the UART signal into an RS232 level, an RS485 level or an RS422 level; and the analog switch module converts the RS422 signal into a half-duplex RS485 signal protocol mode at the level conversion module. According to the invention, flexible switching of three serial communication protocols of RS232, RS485 and RS422 can be realized, and communication requirements of different application scenarios can be met.

This application provides a voltage-controlled resistor (VCR) adjustable termination resistor circuit and system based on mirror control, relating to the field of high-speed serial transmitter design technology. It includes: a working path, a mirror path, and a control loop; the mirror path and the working path operate in the same environment; the control loop applies control voltages to the VCR in the working path and the mirror VCR in the mirror path respectively to control their resistance values; the control loop compares the critical node voltage at the output of the mirror VCR with the reference voltage of a reference voltage source, and outputs a control voltage based on the real-time voltage deviation. The voltage-controlled resistor (VCR) adjustable termination resistor circuit and system provided in this application uses a mirror backup termination resistor to detect the impedance of the termination resistor in real time, and adjusts the termination resistor value in real time when the chip voltage and temperature change, to meet the termination resistor requirements of the high-speed serial interface.

A data transmission chip and an electronic device are provided, and belong to the field of electronic technologies. A high-speed asynchronous serial interface is configured to: receive a first signal from the one or two signal lines, wherein the first signal carries at least one low-speed signal; and transmit the at least one low-speed signal to a corresponding at least one low-speed interface, wherein a data transmission rate of the high-speed serial interface is higher than a data transmission rate of the at least one low-speed interface.

The application relates to the field of next-generation information network industry, and specifically discloses a 5G mainboard fault self-diagnosis method based on AI, which comprises the following steps: selecting standard samples of multiple batches of 5G mainboards, building a full-working-condition gradient test environment, collecting effective eye pattern data of different high-speed serial interfaces, and performing statistical calculation to obtain a three-dimensional dynamic baseline library; collecting real-time eye pattern data of a mainboard to be diagnosed, forming a multi-dimensional fusion feature set through steady-state deviation analysis and dynamic deterioration feature extraction; generating an adaptive threshold set in combination with real-time working conditions, adopting double logic judgment of static feature over-standard and dynamic deterioration constraint to determine suspected fault interfaces; utilizing a Pearson linear correlation coefficient to identify fault deterioration interfaces, quantifying the risk of the fault deterioration interfaces, constructing a differentiated early warning mechanism and fault type judgment according to fault risk values, and realizing early identification, positioning and hierarchical disposal of latent faults of high-speed serial interfaces of the 5G mainboard.

The invention belongs to the technical field of semiconductor device detection and analysis, and discloses a non-contact single event effect evaluation method and system for an FPGA embedded high-speed serial interface. The method comprises the following steps: configuring an FPGA high-speed serial interface link and starting data transmission, and monitoring an error rate and a clock data recovery state at the same time; a capacitive coupling type non-contact probe is suspended above the link differential wiring, and a probe gap is determined through calibration; collecting waveform, eye pattern and frequency spectrum characteristics as baseline data under a non-irradiation condition; operating a link under an irradiation condition, and setting a trigger condition based on error code mutation, lock losing or eye pattern height reduction; probe waveforms and FPGA state parameters are synchronously stored during triggering; and performing single event effect event identification and classification on the waveform data under irradiation by using a convolutional neural network model trained based on baseline data. According to the invention, non-contact and multi-dimensional evaluation of the single event effect of the high-speed serial interface is realized.

This invention belongs to the field of data converter technology, specifically an ADC chip suitable for 128-beam direct sampling phased array receivers. This chip adopts a multi-channel parallel architecture, integrating 128 analog-to-digital conversion channels, each with a sampling rate ≥5 GSPS and a resolution of 12 bits. It includes a sample-and-hold circuit, a quantizer, a digital down-conversion module, and a high-speed serial interface. The clock distribution network uses an H-tree structure to provide a low-jitter sampling clock. The digital down-conversion module down-converts the sampled signal to baseband, and the high-speed serial interface enables high-speed data output. This chip supports direct sampling in the S / Ku / Ka bands, integrating 128 channels on a single chip, significantly simplifying the phased array receiver structure, reducing system complexity and power consumption, and adapting to the application requirements of fully digital phased array receivers.

The application provides a general test sampling circuit for a high-speed serial IO interface receiving end, which comprises a first low-pass filter, a second low-pass filter, a first RX test sampling circuit, a second RX test sampling circuit, a first comparator, a second comparator, and an RX test bias circuit for providing reference voltage and bias voltage for the two RX test sampling circuits and the two comparators; the general test sampling circuit can respectively test and sample each of two differential signal paths of the high-speed serial IO interface receiving end, and judge whether short circuit, open circuit exists in the PCB circuit board, the pressure welding point and the IO according to the received signal. The general test sampling circuit is suitable for the differential receiving end in the high-speed data transmission rate serial interface (above 10G baud rate), and can work in direct current mode and alternating current mode through mode selection signal, and can sample direct current signal and alternating current signal.