Linear equalizer applicable to high-speed serial interface

A high-speed serial interface, linear equalizer technology, applied in the direction of shaping network, baseband system, digital transmission system, etc. The effect of reducing the layout area

Active Publication Date: 2016-12-07
58TH RES INST OF CETC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The trade-off between gain and bandwidth limits the applica...

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  • Linear equalizer applicable to high-speed serial interface
  • Linear equalizer applicable to high-speed serial interface
  • Linear equalizer applicable to high-speed serial interface

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Embodiment Construction

[0027] The embodiments listed in the present invention are only used to help understand the present invention, and should not be interpreted as limiting the protection scope of the present invention. For those of ordinary skill in the art, they can also Improvements and modifications are made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0028] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0029] The invention introduces the inductance peaking technology, utilizes the resonance between the inductance and the output node capacitance, and further expands the bandwidth. image 3 It is a linear equalizer suitable for a high-speed serial interface of the present invention, including a differential input pair consisting of a first NMOS transistor M1 and a second NMOS transistor M2; Bias current...

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Abstract

The present invention relates to a linear equalizer applicable to a high-speed serial interface, comprising a differential input pair transistor consisting of a first NMOS transistor M1 and a second NMOS transistor M2, a bias current source consisting of a third NMOS transistor M3 and a fourth NMOS transistor M4, a pair of differential input signals VINP and VINN, and a pair of differential output signals VOUTP and VOUTN. The linear equalizer further comprises a capacitance-resistance negative feedback equalizer circuit consisting of a variable resistor RS and a variable capacitor CS and an active inductor consisting of a resistor RG and a fifth NMOS transistor M5, which form an output load together with two load resistors RL. According to the linear equalizer applicable to a high-speed serial interface, an active inductor can generate a null point higher than channel bandwidth, and provide broader bandwidth and a greater high-frequency gain in a high-speed serial data transmission process, so that equalizer performance is improved, and a chip area of an integrated circuit chip is effectively reduced, thereby reducing power consumption.

Description

technical field [0001] The invention relates to a linear equalizer suitable for high-speed serial interfaces, belonging to the technical field of integrated circuit design and signal integrity. Background technique [0002] In the field of high-speed signal transmission, compared with the synchronization problem between queues and the influence of crosstalk noise in parallel communication, serial communication has become the mainstream technology for high-speed data transmission due to its low cost and excellent anti-interference performance. As the transmission data rate becomes faster and faster, higher requirements are placed on the transmission bandwidth. [0003] A serializer-deserializer (SerDes, Serializer / Deserializer) is a typical representative of a serial link. figure 1 It is a structural block diagram of a serializer-deserializer (SerDes), which mainly introduces the working principle of a high-speed serial interface circuit. In the transmitting end, a phase-lo...

Claims

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Application Information

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IPC IPC(8): H04L25/03
CPCH04L25/03878
Inventor 杨霄垒蒋颖丹张沁枫杨俊浩
Owner 58TH RES INST OF CETC
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