Design method of asynchronous block cipher algorithm coprocessor
A block cipher algorithm and coprocessor technology, applied in the direction of electric digital data processing, special data processing application, encryption device with shift register/memory, etc. Problems such as low ability
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[0040] figure 1 For adopting the present invention to carry out the design flowchart of asynchronous block cipher algorithm coprocessor, mainly comprise the following steps:
[0041] 1. Divide the block cipher algorithm into sub-modules to obtain sub-modules;
[0042] 2. Sub-module design, including the following steps:
[0043] 2.1 HDL design, get the HDL code of the sub-module.
[0044] 2.2 Logically synthesize the HDL code of the sub-module to obtain the static monorail netlist of the sub-module.
[0045] 2.3 Convert the static single-rail netlist into a netlist composed only of complementary two-input AND gates and OR gates to obtain a composite logic netlist.
[0046] 2.4 Add a delay matching module with the same delay as the sub-module to ensure that the delay from any input signal to the output signal of each sub-module is the same, and the arrival time of any two inputs in the circuit is the same as the two inputs of the gate and the OR gate .
[0047] 3. Integrat...
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