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Design method of asynchronous block cipher algorithm coprocessor

A block cipher algorithm and coprocessor technology, applied in the direction of electric digital data processing, special data processing application, encryption device with shift register/memory, etc. Problems such as low ability

Inactive Publication Date: 2009-01-21
NAT UNIV OF DEFENSE TECH
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, compared with the above constant power consumption logic units such as logic units based on sensitive amplifiers, the constant power consumption characteristics of asynchronous circuits are relatively poor, that is, the protection ability is relatively low
Compared with synchronous circuits, the most significant advantage of asynchronous circuits lies in their low power consumption. The low power consumption design and implementation technology based on asynchronous circuits is also the frontier research content in the field of integrated circuits; but asynchronous circuits do not have computing performance and chip Advantages in terms of area
In addition, the realization of asynchronous circuits is relatively difficult, and there is a lack of mature auxiliary design tools
At present, there is no public report on the asynchronous block cipher algorithm coprocessor that adopts asynchronous circuit design to realize high anti-power attack protection ability, high computing performance and low power consumption.

Method used

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  • Design method of asynchronous block cipher algorithm coprocessor

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Embodiment Construction

[0040] figure 1 For adopting the present invention to carry out the design flowchart of asynchronous block cipher algorithm coprocessor, mainly comprise the following steps:

[0041] 1. Divide the block cipher algorithm into sub-modules to obtain sub-modules;

[0042] 2. Sub-module design, including the following steps:

[0043] 2.1 HDL design, get the HDL code of the sub-module.

[0044] 2.2 Logically synthesize the HDL code of the sub-module to obtain the static monorail netlist of the sub-module.

[0045] 2.3 Convert the static single-rail netlist into a netlist composed only of complementary two-input AND gates and OR gates to obtain a composite logic netlist.

[0046] 2.4 Add a delay matching module with the same delay as the sub-module to ensure that the delay from any input signal to the output signal of each sub-module is the same, and the arrival time of any two inputs in the circuit is the same as the two inputs of the gate and the OR gate .

[0047] 3. Integrat...

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Abstract

The invention discloses a method for designing an asynchronous block cipher algorithm coprocessor, wherein the technical problem which should be solved is to provide the method for designing the asynchronous block cipher algorithm coprocessor. The technical scheme comprises: taking each round of iteration in the block cipher algorithm as an independent submodule, adopting HDL to design each submodule, carrying out logic synthesis to each submodule, obtaining a static monorail net list, transforming the static monorail net list into a composite logic net list which is composed of two inputs which are complementary and doors and / or the doors, carrying out delay matching to each submodule, adding a delay matching module with same delay with the submodule, guaranteeing that the delays of signal input to signal output of each submodule are same, guaranteeing that the input reach time with the doors and / or the doors is same, connecting each submodule in turn, obtaining a complete net list, carrying out rear placement and routing, and obtaining a GDS layout. The coprocessor which is designed through adopting the method has higher power consumption attack resisting and protection ability and simultaneously has high operation performance and low power consumption features.

Description

technical field [0001] The invention relates to a design method of a microprocessor, in particular to a design method of a cryptographic algorithm co-processor. Background technique [0002] The security of cryptographic algorithms includes two aspects, one is the security in the mathematical sense of cryptographic algorithms, and the other is the security in the implementation of cryptographic algorithms. Traditional cryptanalysis is a cracking method aimed at the cryptographic algorithm itself, such as differential and linear cryptanalysis. Conventional cryptanalysis and brute force cracking are ineffective for existing widely used cryptographic algorithms. The power consumption attack is an effective method to crack the key by using the weak link in the specific implementation of the cryptographic algorithm, and it is the attack method with the highest security threat in the side-channel attack. Because there is a statistical correlation between the private key in the se...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50H04L9/06
Inventor 王志英童元满陆洪毅任江春王蕾戴葵龚锐石伟阮坚李勇
Owner NAT UNIV OF DEFENSE TECH
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