The invention discloses a method for designing an asynchronous
block cipher algorithm coprocessor, wherein the technical problem which should be solved is to provide the method for designing the asynchronous
block cipher algorithm coprocessor. The technical scheme comprises: taking each round of iteration in the
block cipher algorithm as an independent submodule, adopting HDL to design each submodule, carrying out
logic synthesis to each submodule, obtaining a static
monorail net
list, transforming the static
monorail net
list into a composite logic net
list which is composed of two inputs which are complementary and
doors and / or the
doors, carrying out
delay matching to each submodule, adding a
delay matching module with same
delay with the submodule, guaranteeing that the delays of
signal input to
signal output of each submodule are same, guaranteeing that the input reach time with the
doors and / or the doors is same, connecting each submodule in turn, obtaining a complete net list, carrying out rear placement and routing, and obtaining a GDS
layout. The
coprocessor which is designed through adopting the method has
higher power consumption
attack resisting and protection ability and simultaneously has high operation performance and low
power consumption features.