121results about How to "Low Power Features" patented technology

A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device

A charge pump power converter efficiently provides electrical power by dynamically controlling a switch matrix of the charge pump. Instead of open-loop oscillator-based control, a dynamic controller provides power upon demand by sensing the output voltage and changing the operating frequency of the charge pump in response. Moreover, this closed-loop dynamic control intrinsically voltage regulates the output voltage of the charge pump power converter without the inefficient addition of a step-down voltage regulator, downstream of the power converter. In addition, this closed-loop dynamic control allows for maintaining a desired output voltage even with variations in the input voltage. Also, the dynamic control accommodates the advantages of using ultra-capacitors in the charge pump. The power converter is capable of operating with a sub-one volt input voltage incorporating low-threshold, low on-resistance power MOSFET switches in the switch matrix of the charge pump. A progressive start-up circuit further allows the power converter to start from a discharged state even with a sub-one volt input voltage.

Disclosed herein is an apparatus and method for low power local area communication using event signal control. The low power local area communication apparatus includes at least one coordinator and a plurality of network device. The network coordinator transmits a periodic beacon signal based on the preset beacon period of a superframe and a continuous RF event signal, receives a first signal including a Service Set Identifier (SSID) and a second signal including the SSID and an event detection code, and performs the transmission or reception of data when authentication has been completed. Each of the network devices generates and transmits the first and second signals, performs the transmission and reception of data after authentication has been completed, and is thereafter switched to power saving mode or OFF mode. Accordingly, the construction of the system is simplified, and the cost of the system is reduced.

The invention relates to a non-vehicle-mounted intelligent DC charging pile, and the charging pile comprises an electric-field type 3D gesture input and LCD display interface, a card reader, a control part, and an AC/DC conversion part. The AC/DC conversion part is an executing mechanism for generating DC power supplied to an electric car, and consists of a BSM auxiliary power supply, an intelligent-type voltage resonance switching power supply, and a protection unit. The card reader achieves the confirmation of a user identity and a payment function. The control part consists of an RISC main control unit, a vehicle type recognition system, a BMS communication system, a GPS module, a comprehensive measurement module, and a cloud access unit. The vehicle type recognition system achieves the visual recognition and confirmation of the type of a to-be-charged car, and transmitting the recognition results to the RISC main control unit, thereby determining a power supply voltage level needed by the BMS of the car, and controlling the BSM auxiliary power supply of the AC/DC conversion part to generate direct current at the power supply voltage level for reliably supplying power to the BMS of the electric car. The image information of the vehicle type recognition system is uploaded to a remote cloud terminal through a cloud access unit.

A display device of the invention includes horizontal lines, longitudinal lines, electron emission elements, and a scanning circuit which performs the selection of the horizontal lines. The scanning circuit includes a non-selection voltage switch, a correction selection voltage switch, and an output voltage detection switch for the selected horizontal line for every horizontal line. The display device also includes a differential amplifier which is connected to a correction selection voltage input line, a horizontal line selection voltage line, and a correction selection voltage output line for every plurality of horizontal lines. The invention can suppress a voltage drop of the horizontal lines and, at the same time, can suppress the brightness irregularities of the display device.

A thin film transistor substrate includes a first thin film transistor disposed having a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode and a first drain electrode; a first gate insulating layer between the polycrystalline semiconductor layer and the first gate electrode; a second thin film transistor disposed having an oxide semiconductor layer on the first gate electrode, a second gate electrode on the oxide semiconductor layer, a second source electrode and a second drain electrode; an intermediate insulating layer disposed on the first gate electrode and under the oxide semiconductor layer; and a second gate insulating layer on the intermediate insulating layer and under the first source electrode, the first drain electrode and the second gate electrode.

The invention discloses an antimonide transistor with high electron mobility, which comprises a substrate, a composite buffer layer, an antimonide lower barrier layer, a channel layer, an antimonide isolated layer, a doping layer, an upper barrier layer and a cap layer, wherein the composite buffer layer grows on the substrate; the antimonide lower barrier layer grows on the composite buffer layer; the channel layer grows on the antimonide lower barrier layer; the antimonide isolated layer grows on the channel layer; the doping layer grows on the antimonide isolated layer; the upper barrier layer grows on the doping layer; and the cap layer grows on the upper barrier layer. The invention discloses a method for manufacturing the antimonide transistor with the high electron mobility. In the antimonide transistor, by adopting the composite buffer layer, the quality of transistor structural materials is improved greatly, the electronic transport characteristic of a channel is better, the output characteristic of the device is improved, the characteristics of high frequency, high speed and low power consumption of the device is fully played, and the stability and reliability of the device are improved effectively.

The invention discloses a seabed heat flow long-term observation probe based on an underwater robot platform. The seabed heat flow long-term observation probe comprises a support probe lever and a plurality of self-capacitance temperature measuring units. The self-capacitance temperature measuring units are helically distributed at equal distance and fixed on the support probe lever to form a distributed multipoint temperature measuring structure, and temperature fluctuation of sediments in different depths of the seabed is observed in the long term. Each self-capacitance temperature measuring unit comprises a housing, a battery, a temperature measuring circuit board, a sensor packaging probe and a temperature sensor, wherein the battery and the temperature measuring circuit board are mounted in the housing, the sensor packaging probe is fixed at one end of the housing, and the temperature sensor is mounted in the sensor packaging probe and electrically connected with the temperature measuring circuit board. The temperature sensors closely contact with the sediments in the seabed, the self-capacitance temperature measuring units helically distributed guarantee that each temperature sensor can contact undisturbed sediments, and fastness and accuracy in temperature measurement of the sediments are guaranteed to the greatest extent.

The invention discloses a method for designing an asynchronous block cipher algorithm coprocessor, wherein the technical problem which should be solved is to provide the method for designing the asynchronous block cipher algorithm coprocessor. The technical scheme comprises: taking each round of iteration in the block cipher algorithm as an independent submodule, adopting HDL to design each submodule, carrying out logic synthesis to each submodule, obtaining a static monorail net list, transforming the static monorail net list into a composite logic net list which is composed of two inputs which are complementary and doors and/or the doors, carrying out delay matching to each submodule, adding a delay matching module with same delay with the submodule, guaranteeing that the delays of signal input to signal output of each submodule are same, guaranteeing that the input reach time with the doors and/or the doors is same, connecting each submodule in turn, obtaining a complete net list, carrying out rear placement and routing, and obtaining a GDS layout. The coprocessor which is designed through adopting the method has higher power consumption attack resisting and protection ability and simultaneously has high operation performance and low power consumption features.

The invention relates to the field of radar communication, in particular, a low profile miniaturized phased array antenna is realized in a three-dimensional integrated manner, comprises an antenna TRmodule and a power supply and differentiator module, the high frequency signal interconnection between the antenna tr module and the power supply and differentiator module is implemented using radio frequency vertical interconnection, A low frequency interconnect is implement using a low frequency pin, the antenna TR module comprises an antenna TR module cavity, Antenna TR module printed circuit board and wave control PCB board, A printed circuit board of the antenna TR module and a waveform control PCB are respectively arranged on both sides of the cavity of the antenna TR module, As that microwave multilayer PCB board is use, the vertical interconnection between layers is realize, thereby realizing ultra-small longitudinal dimension integration, vertical interconnection blind insertion mode is adopted between the soft substrate part of the summer module and the prin circuit board of the antenna TR module, and the radio frequency traces are reduced by using the vertical interconnection between layers inside the microwave multilayer board.

The invention discloses a variable gain low-noise driving amplifier. The amplifier has a fully differential cascode structure, wherein a common gate consists of three side-by-side silicon germanide bipolar transistors; the central silicon germanide bipolar transistor adopts parallel capacitive feedback, a reasonable input/output matching circuit is adopted, a high variable gain is provided for a circuit, and the noise coefficient is reduced; a cascade circuit provides a high variable gain and increases the reverse isolation of the circuit at the same time; and a common source amplifying circuit further improves the gain of the circuit. By controlling the selection of an external bias, the variable gain with a 3dB step length is obtained. The variable gain low-noise driving amplifier has the characteristics of high variable gain, low noise and low power consumption.

A resistive memory device includes a first electrode layer, a second electrode layer, and a first variable resistive layer and a second variable resistive layer stacked at least once between the first electrode layer and the second electrode layer. The first variable resistive material layer may include a metal nitride layer having a resistivity higher than that of the first electrode layer or the second electrode layer and less than or equal to that of an insulating material.

The invention discloses a method for guaranteeing the reliability of data collection transmission in a wireless sensor network, which comprises: adopting a high reliable network organizing method on the basis of dynamic working period adjustment by each sensor node in a sensor network and adopting a high reliable data transmission method on the basis of 2 phase retransmission between sensor nodes and between convergent nodes in the sensor network. On the aspect of network organization reliability guarantee, working modes of the sensor nodes are divided into two modes of normal work and network repair, intermittent working of the nodes under the two modes can be guaranteed through the dynamic working period adjustment, thereby guaranteeing the node lower power consumption characteristics and rapid network repair ability simultaneously. On the aspect of data transmission reliability guarantee, the high reliable data transmission method on the basis of 2 phase retransmission is adopted to guarantee the data integrity when data transmission errors and even chain interruption appear, and the influence of the data transmission errors on the data real time performance is lowered to the minimum.

The invention relates to a passive intelligent electronic lock based on NFC (Near-Field Communication) electromagnetic field charging, and is designed by aiming at the technical problem that an existing intelligent lock product using an NFC technology needs battery or external power supply. The passive intelligent electronic lock consists of a casing, an NFC antenna, a circuit board and a switch lock executing mechanism, wherein the NFC antenna is arranged on the casing; the circuit board is arranged in the casing and is connected with the NFC antenna; and the switch lock executing mechanism is connected with the circuit board. The passive intelligent electronic lock is characterized in that the casing is made of non-metallic materials; the NFC antenna is arranged at the surface of the casing; the circuit board is provided with a control unit, an NFC data communication unit and temporary energy storage units; the switch lock executing mechanism comprises an unlocking/locking executingunit, a state detection unit, a locking clamp buckle and a standby unlocking mechanism; and the temporary energy storage units are conventional capacitors and circuits thereof, so that in the communication connection process, the NFC data communication unit performs energy collection and storage on an NFC signal electromagnetic field provided by upper end equipment with an NFC function, and provides energy for the action of the unlocking/locking executing unit.

The invention provides a large-mismatch silicon-based substrate antimonide transistor with high electron mobility. The large-mismatch silicon-based substrate antimonide transistor comprises a substrate, a composite buffering layer growing on the substrate, an insert layer growing on the composite buffering layer, an AlSb isolation layer growing on the insert layer, a sub channel layer growing on the AlSb isolation layer, an antimonide lower potential barrier layer growing on the sub channel layer, an InAs channel layer growing on the antimonide lower potential barrier layer, an antimonide isolation layer growing on the InAs channel layer, a doping layer growing on the antimonide isolation layer, wherein the doping layer is InAs doped with a Si plane or delta doping of Te; an upper potential barrier layer growing on the doping layer, wherein the upper potential barrier layer is a composite potential barrier layer consisting of an AlSb layer and an InAlAs layer; and an InAs cap layer growing on the upper potential barrier layer, wherein the InAs cap layer is an unintentionally doped InAs or n type doped InAs.

The invention discloses a method for realizing high-speed and safe server cluster management through FPGA virtualization deployment, and belongs to the field of high performance data processing, whichcan improve the speed, the reliability and the safety of services such as access, programming and calculation of small and medium-sized enterprise server clusters for externally deploying FPGA resources a. The method is characterized in that a Docker container engine and a Kubernetes cluster container orchestration engine management system are adopted to construct FPGA virtualization deployment;available virtualized FPGA resources are automatically provided for users outside the cluster in a micro-service mode; then, when a user accesses the virtualized FPGA container, the user can obtain access permission to all resources of FPGA hardware, that is, an operating system kernel of the host machine is directly used to process mass data, and after the user finishes using, the system can automatically release and recycle the resources for next resource allocation and use.

A wireless communication method using a control channel between wireless communication devices including: exchanging profile information between a node and intermediate relay nodes therearound so as to allow the node to transmit/receive data to/from a destination node; determining, by the node, a first intermediate relay node using the profile information and determining a wireless communication mode with the first intermediate relay node; and transmitting/receiving data between the node and the first intermediate relay node by the determined wireless communication mode is provided.

The invention discloses an intelligent BMS structure of lithium battery replacing lead acid battery, which comprises a central processing unit, a collection device, a startup and electric quantity display unit and an electric quantity conversion unit, which are respectively bidirectionally connected with the central processing unit. The collecting unit collects and processes the battery pack unitvoltage, current, temperature and insulation parameters of the battery pack, and uploads them to the central processing unit for data processing. The startup and electric quantity display unit is provided with an auxiliary switch for controlling the closing and opening of the switch unit of the battery pack. The electric quantity conversion unit causes the whole vehicle to accept and display the correct electric quantity value; The switch used in the switch unit of the battery pack is a relay switch. The invention is more suitable for the working condition of high load and high current of theelectric energy demand terminal, and ensures low power consumption, safety and stable operation. The invention provides a method for converting the electric quantity display so as to realize that theelectric quantity can be displayed correctly after the electric energy demand end of the lead-acid battery of the original device is replaced by the lithium battery.

The invention discloses a carbon nanotube field effect transistor (CNFET) type double-edge pulse type JKL trigger. The CNFET type double-edge pulse type JKL trigger comprises a double-edge pulse signal generator, thirty-first CNFET tubes, six NTI gate circuits with the same circuit structure, six PTI gate circuit with the same circuit structure, a first ternary phase inverter and a second ternary phase inverter, wherein the first ternary phase inverter and the second ternary phase inverter have the same circuit structure. The CNFET type double-edge pulse type JKL trigger has the advantages: a clock signal is generated by utilizing the double-edge pulse signal generator; by combining switching operation of a multi-value logic circuit and high-speed low-power features of CNFET, a purpose of reducing the power consumption is achieved when the working speed of the JKL trigger is improved; and based on experiment results, the JKL trigger provided by the invention has a correct logic function and remarkable characteristic of low power consumption.