38results about How to "Correct logic function" patented technology

The invention discloses a tri-valued, thermal-insulating and low-power adder unit and an adder. The adder unit controls each NMOS tube in an input signal sampling circuit to sample input signals by using a clock-controlled clock signal; four corresponding summing circuit modules and carry output circuits with cross storage-type structures are constructed by sampled values according to required realized addition logic relationship through the bootstrap operation of the NMOS tube; power clocks phi1 and phi complete the evaluation and energy recovery of the output load to realize correct logic function; and compared with a DPL tri-valued adder, the four-digit tri-valued thermal-insulating and low-power adder can save energy consumption by about 90 percent in 0.9 microsecond, and has distinct low-power characteristics.

The invention discloses a tri-valued, thermal-insulating and low-power multiplier unit and a multiplier. The multiplier unit controls each NMOS tube in an input signal sampling circuit to sample input signals by using a clock-controlled clock signal; four corresponding integrating circuit modules and carry output circuits with cross storage-type structures are constructed by sampled values according to required realized multiplication logic relationship through the bootstrap operation of the NMOS tube; power clocks phi1 and phi complete the evaluation and energy recovery of the output load to realize correct logic function; and compared with a DPL tri-valued multiplier, the four-digit tri-valued thermal-insulating and low-power multiplier can save energy consumption by about 91 percent in 0.9 microsecond and has distinct low-power characteristics.

The invention discloses a multidigit three-valued low power consumption domino multiplying unit which comprises a first three-valued heat-insulating domino text operating circuit, a second three-valued heat-insulating domino text operating circuit, a carry signal generating circuit and an original standard signal generating circuit; the first three-valued heat-insulating domino text operating circuit is respectively in circuit connection with the carry signal generating circuit and the original standard signal generating circuit; the second three-valued heat-insulating domino text operating circuit is respectively in circuit connection with the carry signal generating circuit and the original standard signal generating circuit; a low-bit carry signal input end of the carry signal generating circuit is connected with a low-bit carry signal input end of the original standard signal generating circuit. The multidigit three-valued low power consumption domino multiplying unit has the following advantages that the multiplying unit is simple in structure on the basis of guaranteeing correct logic function; in comparision with a regular three-valued domino multiplying unit adopting a direct current source, the power consumption is saved by about 54%; in comparison with the three-valued multiplying unit designed on the basis of double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL), the number of transistors is reduced by about 31%.

The invention discloses a three-valued reversible counter using a carbon nano-field effect transistor. The three-valued reversible counter comprises a low-bit counting unit and n high-bit counting units with the same circuit structure, wherein the low-bit counting unit comprises a three-valued pulse type D trigger, a first alternative selector, a first modulo-1 circuit, and a first modulo-2 circuit; the high-bit counting unit comprises a second three-valued pulse type D trigger, a second alternative selector, a second modulo-1 circuit, a second modulo-2 circuit and a carry / borrow circuit. Thethree-valued reversible counter disclosed by the invention has the advantage that the clock signal of each level of counting unit is input after the clock signal of the former level of counting unit is processed through the carry / borrow circuit, thereby guaranteeing that each level of counting unit only needs to receive the clock signal in the counting time, the redundancy hop of the counter produced by the change of the clock signal is reduced, and the dynamic power consumption of the circuit is lowered.

The invention discloses a novel adiabatic logic gating circuit. A first p-channel metal oxide semiconductor (PMOS) tube, a second PMOS tube, a first n-channel metal oxide semiconductor (NMOS) tube, and a second NMOS tube form an energy recovery circuit with a cross-coupled structure, the source electrode of the first PMOS tube and the drain electrode of the second PMOS tube are parallelly connected to the positive terminal of a power source, the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube are parallelly connected to a clock signal terminal, a first PMOS logic block is bridged between the source electrode of the first PMOS tube and the drain electrode of the first PMOS tube, a second PMOS logic block is bridged between the drain electrode of the second PMOS tube and the source electrode of the second PMOS tube, the first PMOS logic block is provided with at least one positive input signal connecting terminal, and the second PMOS logic block is provided with at least one inverted input signal connecting terminal. The invention has the advantages that: an adiabatic circuit of which the functional characteristics are completely opposite to those of the traditional adiabatic logic circuit is provided, and the first PMOS logic block and the second PMOS logic block consists of PMOS tubes, so that the circuit power consumption can be greatlyreduced.

The present invention discloses a neuron MOS based multi-valued counter unit. The counter unit includes a neuron MOS source follower and at least a control gate connected the neuron MOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the neuron MOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the neuron MOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption. The present invention applies the asynchronous carry-over concept to implement the multi-digit multi-value counter, and it also has been verified by the simulation of P Simulation Program with Integrated Circuit Emphasis (SPICE).

The invention discloses a mixed-value based eight-value heat-insulation addition and subtraction counter, which adopts mixed value technology, multi-threshold MOS pipe control technology and clocked heat insulation technology. The counter mainly comprises an eight-value trigger type positive circulating gate and an eight-value heat insulation carry / borrow circuit, wherein the eight-value trigger type heat insulation positive circulating ate consists of a two-value heat insulation positive circulating circuit and a four-value heat insulation positive circulating circuit, a text operation circuit of the four-value heat insulation positive circulating circuit controls a logic signal generating circuit to generate a four-value logic signal. The counter samples an input signal by utilizing a clocked NMOS pipe, ensures that the output load realizes logical assignment and energy reclamation along with a power clock through a sampling value, a bootstrapped NMOS pipe and a cross storage structure, effectively reduces the power consumption on the premise of ensuring the circuit has correct logical function, and improves the work reliability of the integrated circuit.

The invention discloses a low power consumption multiposition three-valued Domino adder. The adder comprises n-numbered positions of three-valued heat insulation Domino adding units, wherein the k position of three-valued heat insulation Domino adding unit is connected with the low-position carry signal output end of the (k+1) position of three-valued heat insulation Domino adding unit by a heat insulation Domino buffer; the k position of three-valued heat insulation Domino adding unit is also connected with the complementary low-position carry signal output end of the (k+1) position of three-valued heat insulation Domino adding unit by a heat insulation Domino buffer; the ipso position and the signal output end of the j position of three-valued heat insulation Domino adding unit are connected with (n-j)-numbered heat insulation Domino buffers in sequence; the addend signal input end and augend signal input end of the j position of three-valued heat insulation Domino adding unit are connected with (j-1)-numbered heat insulation Domino buffers in sequence; k is equal to 1, 2,......, n-1; j is equal to 1, 2,......, n; and m is equal to 1, 2,......, n-1. The adder has the following advantage: the power consumption is reduced by about 61% compared with that of the conventional three-valued Domino adder adopting the direct-current power source.

The invention discloses a tri-valued, thermal-insulating and low-power multiplier unit and a multiplier. The multiplier unit controls each NMOS tube in an input signal sampling circuit to sample input signals by using a clock-controlled clock signal; four corresponding integrating circuit modules and carry output circuits with cross storage-type structures are constructed by sampled values according to required realized multiplication logic relationship through the bootstrap operation of the NMOS tube; power clocks phi1 and phi complete the evaluation and energy recovery of the output load torealize correct logic function; and compared with a DPL tri-valued multiplier, the four-digit tri-valued thermal-insulating and low-power multiplier can save energy consumption by about 91 percent in0.9 microsecond and has distinct low-power characteristics.

The invention discloses a multi-order ternary double-track domino comparator. The multi-order ternary double-track domino comparator consists of at least two-order ternary low-power-consumption domino comparison units; each comparison unit comprises a first control circuit, a second control circuit and a comparison signal generation circuit; and the first control circuit and the second control circuit are respectively used for controlling generation of signals of logics 2 and 1. A comparison result of a high-order ternary low-power-consumption domino comparison unit serves as a high-order comparison output signal which is connected to a low-order ternary low-power-consumption domino comparison unit, a complementary comparison result of the high-order ternary low-power-consumption domino comparison unit serves as a complementary high-order comparison output signal which is connected to the low-order ternary low-power-consumption domino comparison unit, and the high-order comparison output signal and the complementary high-order comparison output signal, which are connected to the highest-order ternary low-power-consumption domino comparison unit, are the logic 1. The multi-order ternary double-track domino comparator has the advantages of correct logic function and simple structure. Compared with the conventional multi-order ternary domino comparator, the multi-order ternary double-track domino comparator has the obvious characteristic of low power consumption, and about 71.4 percent of power consumption is saved.

The invention discloses a four-value heat-insulating dynamic D trigger. The D trigger comprises a character computing circuit, a character sampling circuit and a logic signal generating circuit, wherein the character computing circuit mainly comprises first, second, third and fourth sub-character computing circuits; and the logic signal generating circuit mainly comprises a 0-3 logic signal generating circuit and a 1-2 logic signal generating circuit. The trigger is characterized in that: the four-value heat-insulating dynamic D trigger designed through clocked heat insulation technology and multi-threshold MOS tube control technology mainly comprises the character computing circuit and the logic signal generating circuit; and the logic signal generating circuit is controlled by the character computing circuit to generate a four-value logic signal. The circuits of the D trigger sample the input signal through a clocked NMOS tube, and the output load realizes assignment and energy through a sampling value, the bootstrap-operated NMOS tube and a follow power clock with a cross storage type structure. The D trigger effectively reduces the power consumption and improves working reliability of the circuit on the premise of guaranteeing the correct logic function of the circuits.

The invention discloses a single-phase clock pass transistor adiabatic logic circuit. The circuit is characterized by comprising a logic assignment circuit and an energy regeneration circuit, wherein the energy regeneration circuit consists of two pMOS transistors, namely a first pMOS transistor and a second pMOS transistor; the source of the first pMOS transistor and the source of the second pMOS transistor are connected in parallel with a power clock end; and the logic assignment circuit consists of four nMOS pass transistors, namely, a fifth nMOS pass transistor, a sixth nMOS pass transistor, a seventh nMOS pass transistor and an eighth nMOS pass transistor. The circuit has the advantages of combining the advantages of the single-phase power clock adiabatic logic (CAL) and complementary pass transistor logic (CPL), only one power clock CLK is needed, an auxiliary clock (CX and CX') alternately controls each stage of logic circuit, and the frequency of the circuit is half that of the power clock CLK; the single-phase power clock is used by a full adder on the basis, so that complexity of the clock circuit is reduced, the clock circuit is easier to generate, and the area of the circuit is greatly reduced; and a 5-2 compressor only consists of the full adder and has a simple and normative circuit structure and can compress more digits at one time.

The invention discloses a tri-valued, thermal-insulating and low-power adder unit and an adder. The adder unit controls each NMOS tube in an input signal sampling circuit to sample input signals by using a clock-controlled clock signal; four corresponding summing circuit modules and carry output circuits with cross storage-type structures are constructed by sampled values according to required realized addition logic relationship through the bootstrap operation of the NMOS tube; power clocks phi1 and phi complete the evaluation and energy recovery of the output load to realize correct logic function; and compared with a DPL tri-valued adder, the four-digit tri-valued thermal-insulating and low-power adder can save energy consumption by about 90 percent in 0.9 microsecond, and has distinctlow-power characteristics.

The invention discloses a double-edge D flip-flop based on N type SABL logic. The double-edge D flip-flop comprises a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a fifth transmission gate, a sixth transmission gate and two N type SABL logical units. The double-edge D flip-flop has the advantages that the two N type SABL logical units and the six transmission gates are adopted for designing the double-edge D flip-flop, in the Cadence environment, by the adoption of a TSMC 0.13-micrometer CMOS technology, analog simulation is performed on the double-edge D flip-flop based on the N type SABL logic, an analog result shows that a circuit has a correct logical function, by analyzing power consumption curves of the double-edge D flip-flop based on the N type SABL logic, it can be known that in every clock period, the power consumption curves of the double-edge D flip-flop are the same, power consumption is constant, and the double-edge D flip-flop has a power balance characteristic and achieves the characteristic of resisting to bypass attacks.

The invention discloses a three-valued reversible counter using a carbon nano-field effect transistor. The three-valued reversible counter comprises a low-bit counting unit and n high-bit counting units with the same circuit structure, wherein the low-bit counting unit comprises a three-valued pulse type D trigger, a first alternative selector, a first modulo-1 circuit, and a first modulo-2 circuit; the high-bit counting unit comprises a second three-valued pulse type D trigger, a second alternative selector, a second modulo-1 circuit, a second modulo-2 circuit and a carry / borrow circuit. Thethree-valued reversible counter disclosed by the invention has the advantage that the clock signal of each level of counting unit is input after the clock signal of the former level of counting unit is processed through the carry / borrow circuit, thereby guaranteeing that each level of counting unit only needs to receive the clock signal in the counting time, the redundancy hop of the counter produced by the change of the clock signal is reduced, and the dynamic power consumption of the circuit is lowered.

The invention discloses a ternary low-power-consumption domino comparison unit. The ternary low-power-consumption domino comparison unit comprises a first control circuit, a second control circuit and a comparison signal generation circuit, wherein the first control circuit and the second control circuit are respectively used for controlling generation of signals of logics 2 and 1. A comparator comprises at least two ternary low-power-consumption domino comparison units, wherein a comparison result of a first complementary value signal and a second complementary value signal, which are output from a high-order ternary low-power-consumption domino comparison unit, serves as a complementary high-order comparison output signal which is connected to a low-order ternary low-power-consumption domino comparison unit. The ternary low-power-consumption domino comparison unit has the advantages of correct logic function and simple structure. Compared with the conventional ternary domino value comparison unit adopting a direct current power supply, the comparator has the obvious characteristic of low power consumption, and the power consumption is saved by about 60 percent.

The invention discloses a ternary adiabatic domino multiplication unit. The unit comprises a first ternary adiabatic domino literal arithmetic circuit, a second ternary adiabatic domino literal arithmetic circuit, a carry signal generating circuit and a standard product signal generating circuit, wherein the first ternary adiabatic domino literal arithmetic circuit is connected with the carry signal generating circuit and the standard product signal generating circuit respectively, the second ternary adiabatic domino literal arithmetic circuit is connected with the carry signal generating circuit and the standard product signal generating circuit respectively, and the low order carry signal input end of the carry signal generating circuit is connected with the low order carry signal input end of the standard product signal generating circuit. The unit has the advantages that the structure is simple under the guarantee of the correct logic function, compared with the conventional ternary domino multiplication unit in which a direct current power supply is adopted, the power consumption of the unit is saved by about 54%, and compared with a ternary multiplication unit based on design of a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit, the amount of transistors is reduced by about 31%.