39results about How to "Correct logic function" patented technology

The invention discloses a three-value PUF unit and circuit realized by using CNFET. The three-value PUF circuit comprises a three-value row decoder, a three-value column decoder, a three-value output circuit and a three-value PUF unit array, the three-value PUF unit array is a 3n row* 3n column matrix formed by arranging 3n*3n three-value PUF units, the three-value PUF unit comprises a first CNFET tube, a second CNFET tube, a third CNFET tube, a fourth CNFET tube,a fifth CNFET tube, a sixth CNFET tube, a seventh CNFET tube, an eighth CNFET tube, a ninth CNFET tube and a tenth CNFET tube tenth; and the three-value PUF unit and circuit has the advantages of realizing a relatively small circuit area on the basis of ensuring a correct logic function, and having relatively good randomness and uniqueness.

The invention discloses a single-phase clock pass transistor adiabatic logic circuit. The circuit is characterized by comprising a logic assignment circuit and an energy regeneration circuit, wherein the energy regeneration circuit consists of two pMOS transistors, namely a first pMOS transistor and a second pMOS transistor; the source of the first pMOS transistor and the source of the second pMOS transistor are connected in parallel with a power clock end; and the logic assignment circuit consists of four nMOS pass transistors, namely, a fifth nMOS pass transistor, a sixth nMOS pass transistor, a seventh nMOS pass transistor and an eighth nMOS pass transistor. The circuit has the advantages of combining the advantages of the single-phase power clock adiabatic logic (CAL) and complementary pass transistor logic (CPL), only one power clock CLK is needed, an auxiliary clock (CX and CX') alternately controls each stage of logic circuit, and the frequency of the circuit is half that of the power clock CLK; the single-phase power clock is used by a full adder on the basis, so that complexity of the clock circuit is reduced, the clock circuit is easier to generate, and the area of the circuit is greatly reduced; and a 5-2 compressor only consists of the full adder and has a simple and normative circuit structure and can compress more digits at one time.

The invention discloses a double-edge D flip-flop based on N type SABL logic. The double-edge D flip-flop comprises a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a fifth transmission gate, a sixth transmission gate and two N type SABL logical units. The double-edge D flip-flop has the advantages that the two N type SABL logical units and the six transmission gates are adopted for designing the double-edge D flip-flop, in the Cadence environment, by the adoption of a TSMC 0.13-micrometer CMOS technology, analog simulation is performed on the double-edge D flip-flop based on the N type SABL logic, an analog result shows that a circuit has a correct logical function, by analyzing power consumption curves of the double-edge D flip-flop based on the N type SABL logic, it can be known that in every clock period, the power consumption curves of the double-edge D flip-flop are the same, power consumption is constant, and the double-edge D flip-flop has a power balance characteristic and achieves the characteristic of resisting to bypass attacks.