Novel adiabatic logic gating circuit

Abstract

The invention discloses a novel adiabatic logic gating circuit. A first p-channel metal oxide semiconductor (PMOS) tube, a second PMOS tube, a first n-channel metal oxide semiconductor (NMOS) tube, and a second NMOS tube form an energy recovery circuit with a cross-coupled structure, the source electrode of the first PMOS tube and the drain electrode of the second PMOS tube are parallelly connected to the positive terminal of a power source, the source electrode of the first NMOS tube and the drain electrode of the second NMOS tube are parallelly connected to a clock signal terminal, a first PMOS logic block is bridged between the source electrode of the first PMOS tube and the drain electrode of the first PMOS tube, a second PMOS logic block is bridged between the drain electrode of the second PMOS tube and the source electrode of the second PMOS tube, the first PMOS logic block is provided with at least one positive input signal connecting terminal, and the second PMOS logic block is provided with at least one inverted input signal connecting terminal. The invention has the advantages that: an adiabatic circuit of which the functional characteristics are completely opposite to those of the traditional adiabatic logic circuit is provided, and the first PMOS logic block and the second PMOS logic block consists of PMOS tubes, so that the circuit power consumption can be greatly reduced.

Description

technical field [0001] The invention relates to a logic gate circuit with low power consumption performance, in particular to a novel adiabatic logic gate circuit. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, especially in the ultra-deep submicron era, power consumption has become a non-negligible limiting factor in VLSI system design. In a traditional static CMOS circuit, when the input signal jumps, the DC power supply charges the capacitance of a certain node to Vdd, which means that the stored signal energy is The energy delivered by the power supply to the circuit node is Obviously, in addition to half of the energy delivered to the nodes, half of the energy is consumed. When the node is pulled low, the charge is released from the node to the ground, that is, half of the energy injected into the node is also consumed. It can be seen that the energy drawn from the power supply is only used once. Therefore,...

AI Technical Summary

Problems solved by technology

In a traditional static CMOS circuit, when the input signal jumps, the DC power supply charges the capacitance of a certain node to Vdd, which means that the stored signal energy is The energy delivered by the power supply to the circuit node is Obviously, in addition to half of the energy delivered to the nodes, half of the energy is dissipated

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