Mixed-value based eight-value heat-insulation addition and subtraction counter

Abstract

The invention discloses a mixed-value based eight-value heat-insulation addition and subtraction counter, which adopts mixed value technology, multi-threshold MOS pipe control technology and clocked heat insulation technology. The counter mainly comprises an eight-value trigger type positive circulating gate and an eight-value heat insulation carry / borrow circuit, wherein the eight-value trigger type heat insulation positive circulating ate consists of a two-value heat insulation positive circulating circuit and a four-value heat insulation positive circulating circuit, a text operation circuit of the four-value heat insulation positive circulating circuit controls a logic signal generating circuit to generate a four-value logic signal. The counter samples an input signal by utilizing a clocked NMOS pipe, ensures that the output load realizes logical assignment and energy reclamation along with a power clock through a sampling value, a bootstrapped NMOS pipe and a cross storage structure, effectively reduces the power consumption on the premise of ensuring the circuit has correct logical function, and improves the work reliability of the integrated circuit.

Description

Technical field

[0001] The invention relates to a counter, in particular to an eight-value adiabatic addition and subtraction counter based on mixed values. Background technique

[0002] Internationally, there is considerable emphasis on the development of high-information-density digital logic systems and the enhancement of their information processing capabilities. One of the important research directions is multi-valued logic. Multi-valued logic circuits can not only reduce the chip area and lead count of the integrated circuit, reduce production costs, but also enable the digital logic system to transmit data multiples in one clock cycle, thereby improving work efficiency. In the past, most researches on multi-valued logic circuits focused on three-valued or four-valued logic circuits, while research on eight-valued logic circuits was relatively rare. However, direct design of eight-valued logic circuits requires a higher power supply voltage, which leads to the design The e...

Examples

Embodiment Construction

[0046] The present invention will be described in further detail below in conjunction with the embodiments of the drawings.

[0047] An eight-value adiabatic addition and subtraction counter based on mixed values ​​(2-4 mixed values), such as Figure 1a As shown, it includes N-bit eight-value trigger adiabatic positive circulation gate 1, N-1 eight-value adiabatic carry / borrow circuit 2 and an eight-value adiabatic carry / borrow circuit set at the i-th bit and the i+1-th eight-value adiabatic carry / borrow circuit. The CTGAL buffer 3 between the value-triggered adiabatic positive circulation gates, the CTGAL buffer makes the phase of the output signal of the i-th octal value adiabatic carry / borrow circuit and the i+1-th octal trigger adiabatic positive circulation gate The phases of the clock-controlled clocks are the same, and each 8-value trigger adiabatic positive circulation gate is connected to the power clock signal with the amplitude level corresponding to logic 1. The amplit...

Technical field

[0001] The invention relates to a counter, in particular to an eight-value adiabatic addition and subtraction counter based on mixed values. Background technique

[0002] Internationally, there is considerable emphasis on the development of high-information-density digital logic systems and the enhancement of their information processing capabilities. One of the important research directions is multi-valued logic. Multi-valued logic circuits can not only reduce the chip area and lead count of the integrated circuit, reduce production costs, but also enable the digital logic system to transmit data multiples in one clock cycle, thereby improving work efficiency. In the past, most researches on multi-valued logic circuits focused on three-valued or four-valued logic circuits, while research on eight-valued logic circuits was relatively rare. However, direct design of eight-valued logic circuits requires a higher power supply voltage, which leads to the design The e...

Examples

Embodiment Construction

[0046] The present invention will be described in further detail below in conjunction with the embodiments of the drawings.

[0047] An eight-value adiabatic addition and subtraction counter based on mixed values ​​(2-4 mixed values), such as Figure 1a As shown, it includes N-bit eight-value trigger adiabatic positive circulation gate 1, N-1 eight-value adiabatic carry / borrow circuit 2 and an eight-value adiabatic carry / borrow circuit set at the i-th bit and the i+1-th eight-value adiabatic carry / borrow circuit. The CTGAL buffer 3 between the value-triggered adiabatic positive circulation gates, the CTGAL buffer makes the phase of the output signal of the i-th octal value adiabatic carry / borrow circuit and the i+1-th octal trigger adiabatic positive circulation gate The phases of the clock-controlled clocks are the same, and each 8-value trigger adiabatic positive circulation gate is connected to the power clock signal with the amplitude level corresponding to logic 1. The amplit...

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