45results about "Counting chain pulse counters using semiconductor devices" patented technology

A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N−1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multi-modulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.

A divided clock signal is generated from an input clock signal. The duty cycle of the divided clock signal is programmed by generating a compare value based on values of duty cycle input and a divide value of the input clock signal. The compare value is compared to a count value to generate short and long pulse signals. The divided clock signal is generated based on the short and long pulse signals. The duty cycle of the divided clock signal varies in accordance with the compare value.

A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is coupled. Retimer flip-flops may be coupled between adjacent flip-flips to resynchronize the signal being coupled through the flip-flops. Each of the retimer flip-flops receives a respective signal from the output of an upstream flip-flop at its data input, and it receives the input clock signal at its clock input. The flip-flop then applies the signal to a downstream flip-flop in synchronism with the input clock signal. The final two flip-flops through which the input signal is coupled may be preset to various states to set the phase of the output clock signal to one of four phases.

A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N−1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multi-modulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.

The invention discloses a latch, a two-frequency divider circuit based on current mode logic and a frequency divider. The latch comprises a first logic unit, a second logic unit and a control unit, wherein the first logic unit comprises a first input end, a second input end, a first output end, a second output end and a clock signal positive input end; the second logic unit comprises a third inputend, a fourth input end, a third output end, a fourth output end and a clock signal negative input end; the first output end is coupled with the third input end and the fourth output end; the secondoutput end is coupled with the third output end and the fourth input end; and the control unit is coupled between the first logic unit and a power supply and between the second logic unit and the power supply, and a current path between the power supply and a ground wire is controlled by resistance regulation. The invention provides a latch with a controllable resistance value at the output end; and the frequency divider realized based on the latch can eliminate the problem of narrow frequency division ranges of existing frequency dividers, and can greatly improve the frequency division rangeof the frequency divider.

A design structure embodied in a machine readable medium includes information for designing, manufacturing and / or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit.

An electronic circuit comprises: an input terminal; an output terminal; first and second supply rails; first, second, third, and fourth field effect transistors, FETs, each of a first type and each having respective gate, source and drain terminals; and first and second loads. The source of the first FET is connected to the first supply rail, the drain of the first FET and the source of the second FET are connected to the output terminal, the drain of the second FET is connected to the second supply rail, the gate of the third FET and the gate of the fourth FET are connected to the input terminal, the drain of the third FET is connected to the second supply rail, the first load is connected between the first supply rail and the source of the third FET, and the second load is connected between the drain of the fourth FET and the second supply rail. In one aspect of the invention, the gate of the first FET is connected to a node between the source of the third FET and the first load such that a voltage at the source of the third FET is applied to the gate of the first FET, and the gate of the second FET is connected to a node between the drain of the fourth FET and the second load such that a voltage at the drain of the fourth FET is applied to the gate of the second FET.

A high speed binary counter includes a counting first flip-flop for each binary bit, a single AND gate for each lower order binary bit beyond B0 and B1, and at least two AND gates for each higher order binary bit. The counter also includes an input factor delay second flip-flop. The counter is further provided with a mechanism for redundant least significant terms for lesser order bits.

A high speed binary counter includes a counting first flip-flop for each binary bit, a single AND gate for each lower order binary bit beyond B0 and B1, and at least two AND gates for each higher order binary bit. The counter also includes an input factor delay second flip-flop. The counter is further provided with a mechanism for redundant least significant terms for lesser order bits.

A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

The invention discloses a three-valued reversible counter using a carbon nano-field effect transistor. The three-valued reversible counter comprises a low-bit counting unit and n high-bit counting units with the same circuit structure, wherein the low-bit counting unit comprises a three-valued pulse type D trigger, a first alternative selector, a first modulo-1 circuit, and a first modulo-2 circuit; the high-bit counting unit comprises a second three-valued pulse type D trigger, a second alternative selector, a second modulo-1 circuit, a second modulo-2 circuit and a carry / borrow circuit. Thethree-valued reversible counter disclosed by the invention has the advantage that the clock signal of each level of counting unit is input after the clock signal of the former level of counting unit is processed through the carry / borrow circuit, thereby guaranteeing that each level of counting unit only needs to receive the clock signal in the counting time, the redundancy hop of the counter produced by the change of the clock signal is reduced, and the dynamic power consumption of the circuit is lowered.

A design structure embodied in a machine readable medium includes information for designing, manufacturing and / or testing a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU'S. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit.

The invention discloses a frequency divider circuit with anti-irradiation function, comprising more than three frequency divider units and a voting unit, wherein the output ends of each frequency divider unit are respectively connected to the input end of the voting unit, and the output end of the voting unit is in feedback connection to the input ends of each frequency divider unit. The frequencydivider circuit has the advantages such as simple structure, low cost, anti-irradiation function and low soft error rate.

The application discloses an anti-single-event upset reinforced CML latch, a frequency division circuit and equipment, the CML latch of the application comprises a latch circuit composed of NMOS transistors, PMOS transistors for inhibiting the "1 to 0" jump of single-event upset are connected to both input sides of the latch circuit, the signal connected to the gate of one PMOS transistor is a frequency division clock signal clk180-o obtained by current mode to CMOS conversion of the 180-degree phase frequency division clock signal clk180 output by the latch circuit, and the signal connected to the gate of the other PMOS transistor is a frequency division clock signal clk0-o obtained by current mode to CMOS conversion of the 0-degree phase frequency division clock signal clk0 output by the latch circuit. The application aims at achieving anti-single-event upset reinforcement for the CML latch with low overhead, and improving the anti-radiation reinforcement performance of the CML latch.

A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

A signal generator produces an output clock signal by coupling an input clock signal through a plurality of divider circuits each of which is formed by a toggling flip-flop. The frequency of the output clock signal is adjusted by selecting the flip-flop to which the input clock signal is coupled. Retimer flip-flops may be coupled between adjacent flip-flips to resynchronize the signal being coupled through the flip-flops. Each of the retimer flip-flops receives a respective signal from the output of an upstream flip-flop at its data input, and it receives the input clock signal at its clock input. The flip-flop then applies the signal to a downstream flip-flop in synchronism with the input clock signal. The final two flip-flops through which the input signal is coupled may be preset to various states to set the phase of the output clock signal to one of four phases.

The embodiment of the invention provides a multi-frequency multiplication circuit for a low-noise frequency synthesizer. The method is applied to the field of frequency synthesizers, and comprises a duty ratio correction module, a second frequency multiplication module and a multi-frequency multiplication module which are connected in sequence, and a first switch, a second switch and a third switch which are respectively connected with the modules in parallel, selection of a signal path is controlled by changing the combination state between the switch assemblies. In this way, the problem that high-density stray is introduced to an output signal frequency spectrum due to the fact that the signal frequency is too low can be solved; when the first switch and the third switch are closed, the reference signal frequency is improved through the exclusive-OR gate frequency multiplier structure, and the phase noise performance is optimized; when the third switch is closed, the duty ratio of the input signal is dynamically calibrated to 50% through the duty ratio correction module, and performance deterioration caused by duty ratio deviation is eliminated; when the first switch and the second switch are closed, the reference frequency is remarkably improved through the frequency multiplier, the reference spurious level is reduced, and compromise optimization of noise and spurious is achieved.

The invention discloses a three-valued addition counter based on CNFETs. The three-valued addition counter comprises a pulse signal generator, n addition counting units, and an n input AND gate. The pulse signal generator has an input end and output end. Each addition counting unit has an input end, an output end, a clock control end, and a carry output end. The n input AND gate has n input ends and an output end. The output end of the pulse signal generator is connected with the clock control ends of the n addition counting units. The carry output ends of the n addition counting units and the n input ends of the n input AND gate are connected in one-to-one correspondence. The output end of the n input AND gate is the carry output end of the three-valued addition counter. The carry output end of the kth addition counting unit is connected with the input end of the (k+1)th addition counting unit, wherein k=1, 2, ..., n-1. The output end of the jth addition counting unit is the jth output end of the three-valued addition counter, wherein j=1, 2, ..., n. The three-valued addition counter reduces invalid operation, decreases circuit power consumption and time delay, and has a high-speed low-power-consumption characteristic.

The invention discloses a millimeter wave high-speed frequency divider, and relates to the field of millimeter wave integrated circuits. The millimeter wave high-speed frequency divider is a frequency divider module applied in a millimeter wave transceiver chip, and solves the technical problems that the existing high-speed frequency divider is too large in area and too narrow in frequency division range. The millimeter wave high-speed frequency divider comprises four simple D triggers connected in sequence into a ring. The millimeter wave high-speed frequency divider not provided with passive devices such as an inductor occupying large area has the technical advantages of small area and large frequency division range.

A counting control circuit includes a logic control circuit and a counting statistic circuit, an output terminal of the logic control circuit is connected to a clock terminal of the counting statistic circuit. The logic control circuit is configured to receive a first clock signal and a first identification signal, and generate a counting clock signal according to the first clock signal under a control of the first identification signal. The counting statistic circuit is configured to receive the counting clock signal, count according to the counting clock signal, and generate the first identification signal which indicates a generation of a command signal for performing a first operation, here, the first identification signal is in a valid state when a counting value meets a preset condition.

The invention discloses an analog frequency divider which comprises a first analog latch and a second analog latch, the output end of the first analog latch is connected with the input end of the second analog latch, and the output end of the second analog latch is connected with the input end of the first analog latch; the analog frequency divider receives analog signals, and the analog signals are amplified and sampled through the first analog latch and the second analog latch so as to realize frequency division of the analog signals. According to the invention, the output end of the first analog latch is connected with the input end of the second analog latch, and the output end of the second analog latch is connected with the input end of the first analog latch, so that the frequency division of the analog signal is realized.

The invention is suitable for the field of frequency dividers, and provides an orthogonal input divide-by-2 frequency divider, which comprises: a filter circuit for inputting an external power supply and performing output after filtering; a tuning circuit connected with an output end of the filter circuit; a mixer stage connected to an output end OUTI, an output end OUTIB, an output end OUTQB and an output end OUTQ of the orthogonal input divide-by-2 frequency divider together with the output end of the filter circuit; a transconductance stage connected with an input end INI, an input end INIB, an input end INQ and an input end INQB of the orthogonal input divide-by-2 frequency divider respectively to input a voltage signal, convert the voltage signal into a current signal and output the current signal to a common source end of the mixer stage; and a current source biasing circuit connected to the common source end of the transconductance stage and enabling the transconductance stage to form a variable current source by injecting an external current source. According to the orthogonal input divide-by-2 frequency divider provided by the invention, the external current source is injected into the current source biasing circuit to enable the transconductance stage to form the variable current source so as to increase the current of the transconductance stage, so that the conversion grain, the degree of linearity and the range of a working frequency of the orthogonal input divide-by-2 frequency divider can be effectively improved.

The disclosure pertains to a toggle flipflop circuitry that includes: a first count switch that is configured to couple an input node to a first output node during a first count signal level, wherein the first count switch is configured to retard a path signal propagation from the first output node to the input node by a predetermined delay; a first inverter that is configured to couple a second output node to the first output node; a first switchable active feedback loop that is configured to selectively propagate a path signal from the input node to the first output node during the first count signal level; a second switchable active feedback loop that is configured to propagate a negation of a path signal from the second output node to the first output node during a second count signal level different from the first count signal level; and a second count switch that is configured to selectively couple the input node to the second output node during the second count signal level.

The invention discloses a CPLD-based clock counting method and device, and a medium. The method comprises the following steps: acquiring an event duration of a CPLD, and setting layers representing counting cycles according to the event duration, wherein the layers at least comprise two layers, the lowest layer represents a system cycle, durations of the counting cycles are positively related to layer levels, and the counting cycle represented by a higher layer is an integer multiple of the counting cycle represented by a lower layer; starting counting by using the counting cycle represented by the lowest of the layers as a current cycle, and using a target counting cycle represented by a next layer as the current cycle to continue the counting when a counting duration reaches the target counting cycle, until the current cycle is identical to the counting cycle represented by the highest of the layers; and continuing the counting according to the current cycle to reach the event duration. Therefore, the method provided by the invention has the beneficial effect that the overall work efficiency of the CPLD during clock counting is relatively improved. Moreover, the invention furtherprovides the CPLD-based clock counting device, and the medium, which achieve the above beneficial effect.

The invention discloses a three-valued reversible counter using a carbon nano-field effect transistor. The three-valued reversible counter comprises a low-bit counting unit and n high-bit counting units with the same circuit structure, wherein the low-bit counting unit comprises a three-valued pulse type D trigger, a first alternative selector, a first modulo-1 circuit, and a first modulo-2 circuit; the high-bit counting unit comprises a second three-valued pulse type D trigger, a second alternative selector, a second modulo-1 circuit, a second modulo-2 circuit and a carry / borrow circuit. Thethree-valued reversible counter disclosed by the invention has the advantage that the clock signal of each level of counting unit is input after the clock signal of the former level of counting unit is processed through the carry / borrow circuit, thereby guaranteeing that each level of counting unit only needs to receive the clock signal in the counting time, the redundancy hop of the counter produced by the change of the clock signal is reduced, and the dynamic power consumption of the circuit is lowered.

Spot splitter (100), which has the following features: two or more spot circuits electrically connected in a ring, and a first single-phase spot circuit (104) having a spot input (YOUR), a spot output (OFF) and a clock input (CLKB), wherein the first single-phase spot circuit (104) has the following: a first input field-effect transistor (FET) (202) with a first polarity, which is electrically connected between a first supply node (VDD) and a signal node (V1), wherein a gate electrode of the first FET (202) is electrically connected to the spot input (DEIN), a first clock FET (206) with a second polarity opposite to the first polarity, a second input FET (212) with the second polarity, which is electrically connected in series with the first clock FET (206) between the signal node (V1) and a second supply node (VSS), a second clock FET (204) with the first polarity, wherein a gate electrode of the first clock FET (206) and a gate electrode of the second clock FET (204) are electrically connected to the clock input (CLKB), and an output FET (208) of the first polarity, which is electrically connected in series with the second clock FET (204) between the first supply node (VDD) and the spot output (OFF), wherein a gate electrode of the output FET (208) is electrically connected to the signal node (V1), wherein the first single-phase spot circuit (104) further comprises at least one of a reset input (RST) or a set input (SB) designed to initialize a state of the first single-phase spot circuit (104).

The disclosure provides a clock step control circuit and a method thereof. The clock step control circuit includes a clock divider, a multiplexer, and a controller. The clock divider receives a first clock signal and outputs multiple second clock signals. The multiplexer receives the second clock signals and outputs one of the second clock signals. The controller is coupled to the clock divider and the multiplexer. When the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal. The multiplexer outputs another one of the second clock signals according to the selection signal. The clock step control circuit and the method thereof in the disclosure can appropriately switch the clock signal to output a clock signal with an appropriate clock frequency.

The invention discloses a broadband injection locking frequency-quad divider, relates to the technical field of radio frequency integrated circuit design, and is used for solving the technical problems that the actual locking bandwidth range of an existing frequency divider is insufficient, and the impedance matching characteristic of a resonant cavity is disturbed by parasitic capacitance of an injection node and distributed parameters. According to the broadband injection-locked quad frequency divider, n injection ring oscillation units are connected in series to form a multi-stage chain type structure, wherein each injection ring oscillation unit is provided with a tail current injection unit and a cross-coupled inverter injection unit; in the chain type structure, the first output end and the second output end of the last stage of injection ring vibration unit are respectively connected with the second input end and the first input end of the first stage of injection ring vibration unit. A first signal is injected into a tail current injection unit and a cross-coupling inverter injection unit of each injection ring oscillation unit, and the last stage of injection ring oscillation unit receives a second signal from the previous stage of injection ring oscillation unit and converts the second signal into a third signal with four frequency divisions to be output.