26results about "Counting chain asynchronous pulse counters" patented technology

The invention relates to the field of pulse signal generation, and discloses an integer frequency signal generation circuit and method for a microprocessor, and the circuit comprises a flipping register, a frequency division register, a counter, a frequency signal flipping module, an integer frequency calculation unit, and a time delay unit. The integer frequency calculation unit is used for calculating the delay series of the fractional part of the frequency division value when the enable signal 1 is valid, and sending the delay series to the delay unit; and the delay unit is used for carrying out delay less than one clock period on the frequency signal output by the frequency signal overturning module according to the delay series sent by the integer frequency calculation unit, and outputting an integer frequency signal. According to the integer frequency signal output circuit disclosed by the invention, the frequency division value and the delay series of the frequency division register are automatically changed through the integer calculation module and the delay series calculation module, and the delay series controls the one-out-of-256 selector to be used for selecting the frequency signal output of the corresponding delay module in the delay unit, so that the generation of the integer frequency signal is realized.

The invention relates to a programmable frequency divider applied to JESD204B / C. The programmable frequency divider comprises a prescaler which realizes 1 / 2 / 4 dynamic frequency division through a closed-loop feedback structure; according to the 12-bit main frequency divider, the duty ratio of odd-even frequency division is controlled by a 11-stage asynchronous CML frequency-halving chain and a separation DFF0 module; the frequency dividing ratio N is equal to DIV Nlt; 11: 0gt; 2, the odd number frequency division duty ratio is automatically adjusted to (N + 1) / 2N; the cascade noise optimization comprises the following steps of: resampling by using an input clock fin through a retiming trigger (RetimeDFF1 / 2); according to the pulse generator, the number K of pulses output by a four-stage counter is equal to Pulsecount; 3: 0gt; a decimal value; and the output mode circuit supports three-mode direct connection. According to the programmable frequency divider, the HBT process CML unit and the emitter follower are adopted for buffering; and the high-precision clock synchronization requirements of JESD204B / C systems such as a 5G base station and a millimeter wave radar can be met.

The invention relates to a fractional divider. The device (110) includes a counter (202) having a clock input, a count value input, a third input, and an output. A multiplexer (218) has a first input, a second input, a selection input, and an output. A delay circuit (210) has a first input coupled to the clock input of the counter (202), a second input coupled to the output of the counter (202), a first output, and a second output. The first output is coupled to the first input of the multiplexer (218), and the second output is coupled to the second input of the multiplexer (218). A fractional control circuit (214) has a first output coupled to the selection input of the multiplexer (218), and has a second output coupled to the third input of the counter (202).

The invention relates to the field of integrated circuits, and discloses a programmable 0.5-frequency-division frequency divider which comprises a programmable integer frequency divider, a coding circuit, a sampling circuit and a selection circuit. The encoding circuit generates a synchronous control signal using a preliminary output of the integer frequency divider itself. In the 0.5 frequency division mode, the circuit periodically switches the frequency division ratio of the frequency divider between N and N + 1, and synchronously switches the selection signal of the post-stage sampling circuit, so that the selection signal alternately selects between the rising edge sampling result and the falling edge sampling result of the input clock. According to the scheme, the structure is simple, only one programmable integer frequency divider is needed, the chip area and the design complexity are remarkably reduced, and meanwhile the development rhythm of the circuit is accelerated through robust internal time sequence control.

The application relates to the field of integrated circuits, and discloses a programmable 0.5 frequency divider, which comprises a programmable integer frequency divider, a coding circuit, a sampling circuit and a selection circuit. The coding circuit utilizes the preliminary output of the integer frequency divider to generate a synchronous control signal. In the 0.5 frequency division mode, the circuit periodically switches the frequency division ratio of the frequency divider between N and N+1, and synchronously switches the selection signal of the subsequent sampling circuit, so that the selection signal alternately selects the sampling results at the rising edge and the falling edge of the input clock. The scheme has simple structure, only needs a programmable integer frequency divider, significantly reduces the chip area and design complexity, and accelerates the development rhythm of the circuit through robust internal timing control.

A counter, an analog-to-digital converter, and a method for reading out image signals; the counter comprises N cascaded counting units, each of which comprises a writable D flip-flop, which has a clock input, a data input, a Q output, a Q-bar output, a control input, and a write input; the clock input of the writable D flip-flop of each counting unit is connected to the Q-bar or Q output of the writable D flip-flop of a previous counting unit, except that the clock input of the writable D flip-flop of a first counting unit of the N cascaded counting units receives a clock signal; the Q-bar output of each writable D flip-flop is connected to the data input of the same writable D flip-flop, each Q output generates a counting result, each control input receives a control signal, and each write input receives a write signal.

The present invention relates to the field of pulse signal generation and discloses a microprocessor integer frequency signal generation circuit and generation method, comprising a flip register, a frequency division register, a counter, a frequency signal flip module, an integer frequency calculation unit, and a delay unit; the integer frequency calculation unit is configured to calculate the delay level of the fractional portion of the frequency division value when an enable signal 1 is valid and send the delay level to the delay unit; the delay unit is configured to delay the frequency signal output by the frequency signal flip module by less than one clock cycle based on the delay level sent by the integer frequency calculation unit and output the integer frequency signal. The integer frequency signal output circuit disclosed in the present invention automatically changes the frequency division value and delay level of the frequency division register through the integer calculation module and the delay level calculation module. The delay level controls a 256-to-1 selector to select the frequency signal output of the corresponding delay module in the delay unit, thereby achieving the generation of the integer frequency signal.

The application relates to a random clock generation method and device against side channel attacks, wherein the method comprises the following steps: S1, selecting a reference clock as an input clock of a first round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; S2, randomly selecting a frequency multiplication clock from the frequency multiplication clocks, performing spur filtering, and then outputting the frequency multiplication clock as a system clock; S3, performing multi-path frequency division on the randomly selected frequency multiplication clock to obtain frequency division clocks with different frequency division coefficients; S4, randomly selecting a frequency division clock from the frequency division clocks, and performing multi-path frequency multiplication on the frequency division clock as an input clock of a next round of multi-path frequency multiplication to obtain frequency multiplication clocks with different frequency multiplication coefficients; and S5, repeating steps S2 to S4, and obtaining a system clock with various and random frequencies through multiple rounds of iteration. The application effectively improves the side channel attack protection effect.

An apparatus includes a counter having a clock input, a count value input, a third input, and an output. A multiplexer has a first input, a second input, a selection input, and an output. A delay circuit has a first input coupled to the clock input of the counter, a second input coupled to the output of the counter, a first output and a second output. The first output is coupled to the first input of the multiplexer, and the second output is coupled to the second input of the multiplexer. A fractional control circuit has a first output coupled to the selection input of the multiplexer and has a second output coupled to the third input of the counter.

The present application provides an image sensor and its readout circuit (1). Among them, the readout circuit (1) of the image sensor consists of a lamp voltage circuit (10), a comparison circuit (20), a counter circuit (30), and an inversion control circuit (40). When switching the count, the inversion control circuit (40) is provided to control the counter circuit (30) to invert from the first digital code value to the second digital code value. Thus, in the second quantization period, the counter circuit (30) counts from the second digital code value to the third digital code value based on the second digital code value, realizing correlated double sampling, removing fixed pattern noise, improving the imaging quality, and in the readout circuit (1), there is no need to provide a buffer and an additional holding circuit, simplifying the circuit structure, reducing power consumption, and ensuring that the counter circuit operates in a high-frequency counting mode.

A semiconductor device according to this disclosure includes: a comparator circuit; a counter circuit; and a latch circuit that stores a count value of the counter circuit at a timing when an output signal of the comparator circuit changes, the counter circuit includes: a multiphase signal generator; and a plurality of flip-flop circuits including a first-stage flip-flop and second-stage and subsequent flip-flops, the first-stage flip-flop takes in an inverted signal of an output signal of a flip-flop in a final stage and each of the second-stage and subsequent flip-flops takes in an output signal of a flip-flop in a preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits is output as a count signal of the count value.

A semiconductor device according to this disclosure includes: a comparator circuit; a counter circuit; and a latch circuit that stores a count value of the counter circuit at a timing when an output signal of the comparator circuit changes, the counter circuit includes: a multiphase signal generator; and a plurality of flip-flop circuits including a first-stage flip-flop and second-stage and subsequent flip-flops, the first-stage flip-flop takes in an inverted signal of an output signal of a flip-flop in a final stage and each of the second-stage and subsequent flip-flops takes in an output signal of a flip-flop in a preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits is output as a count signal of the count value.

The embodiment of the present disclosure provides a counting circuit, comprising: a clock source, a clock control unit and N output units; wherein N is a positive integer. The clock control unit generates a clock control signal according to a clock signal output by the received clock source and output values of the first output unit to the Mth output unit, and outputs the clock control signal to clock input ends of the M+1th output unit to the Nth output unit, wherein the clock control signal has a first signal value and a second signal value with different signal values. The M+1th output unit to the Nth output unit latch when the received clock control signal switches from the second signal value to the first signal value; and keep the current state value unchanged when the received clock control signal is the second signal value.

This invention relates to a programmable frequency divider for JESD204B / C standards. The divider comprises a prescaler that implements dynamic 1 / 2 / 4 frequency division via a closed-loop feedback structure; a 12-bit main divider with an 11-stage asynchronous CML divide-by-two chain and a separate DFF0 module to control the odd-even frequency division duty cycle. The divider ratio N = DIV_N<11:0> + 2, with the odd-numbered frequency division duty cycle automatically adjusted to (N+1) / 2N; cascaded noise optimization with retiming flip-flops (RetimeDFF1 / 2) that resample the input clock fin; a pulse generator with a four-stage counter that outputs a decimal value of the pulse count K = Pulse_count<3:0>; and an output mode circuit that supports three-mode pass-through. This programmable frequency divider utilizes HBT CML cells and emitter-follower buffering, meeting the high-precision clock synchronization requirements of JESD204B / C systems such as 5G base stations and millimeter-wave radars.

To provide a semiconductor device capable of implementing a high quality operation, a control method thereof, and a control program.SOLUTION: A semiconductor device includes a comparator circuit for comparing a measurement target signal with a reference voltage signal whose potential changes periodically and linearly, a counter circuit, and a latch circuit for storing a count value of the counter circuit at a timing when the output signal of the comparator circuit changes. The counter circuit includes a multiphase signal generator for shifting the phase of a reference clock signal to generate a plurality of clock signals having different phases, and a plurality of flip-flop circuits. A first-stage flip-flop captures an inverted signal of an output signal of a last-stage flip-flop, and each flip-flop of the second and subsequent stages captures an output signal of a flip-flop of a previous stage in synchronization with each of the plurality of clock signals, and outputs the output signal of each of the plurality of flip-flop circuits as a count signal of the count value.SELECTED DRAWING: Figure 3

The invention relates to the field of integrated circuits, and discloses a programmable 0.5-frequency-division frequency divider which comprises a programmable integer frequency divider, a coding circuit, a sampling circuit and a selection circuit. The encoding circuit generates a synchronous control signal using a preliminary output of the integer frequency divider itself. In the 0.5 frequency division mode, the circuit periodically switches the frequency division ratio of the frequency divider between N and N + 1, and synchronously switches the selection signal of the post-stage sampling circuit, so that the selection signal alternately selects between the rising edge sampling result and the falling edge sampling result of the input clock. According to the scheme, the structure is simple, only one programmable integer frequency divider is needed, the chip area and the design complexity are remarkably reduced, and meanwhile the development rhythm of the circuit is accelerated through robust internal time sequence control.

This application provides an enable control circuit and a semiconductor memory. The enable control circuit includes: a counting module for counting the current clock cycle and determining a clock cycle count value; a selection module for determining a clock cycle count target value based on a first setting signal; and a control module for controlling the ODT path to be in an enabled state and starting the counting module when the level state of the ODT pin signal flips; and controlling the ODT path to switch from an enabled state to a disabled state when the clock cycle count value reaches the clock cycle count target value and the level state of the ODT pin signal remains unchanged; and controlling the ODT path to remain in an enabled state when the clock cycle count value reaches the clock cycle count target value and the level state of the ODT pin signal flips again. This not only saves power but also solves the problem that the ODT path cannot be enabled when the ODT pin level flips a second time in some cases.

An integrated circuit is provided for processing data in a functional mode and testing the integrated circuit in a scan mode. The integrated circuit comprises a processing unit, a digital function block, an asynchronous counter, an asynchronous counter test stage, a comparator. The processing unit is configured to process and store data in the functional mode of the integrated circuit based on a system clock. The digital function block is implemented by registers and N scan flip-flops, each of which is connected to the system clock. The asynchronous counter is implemented by M flip-flops connected in a chain. The asynchronous counter test stage is configured to reset count data and store test data in the digital function block in preparation for testing the asynchronous counter in a scan mode of the asynchronous counter.

The utility model belongs to the technical field of medical monitoring, and particularly relates to a low-power-consumption respiration induction plethysmography device which comprises an elastic binding belt, a wire coil is arranged on the inner surface of the elastic binding belt, the wire coil is in a wave shape or a sine shape, the elastic binding belt can elastically deform under the action of external force, and the elastic binding belt is connected with the wire coil. The device further comprises a signal processor, the signal processor is connected with the wire coil, the signal processor comprises a signal processing circuit, the signal processing circuit comprises an asynchronous counter, a reverser, an MOS tube and an oscillator, the wire coil is connected with the frequency signal input end of the counter, and meanwhile the signal processor is connected with the signal processing circuit. The lead coil is further connected with the reverse output end and the input end of the phase inverter, the drain electrode of the MOS tube is connected with the GND of the phase inverter, and the gate electrode of the MOS tube is connected with the oscillator. The utility model not only has lower energy consumption, but also has smaller volume.

The objective is to provide a clock modulation circuit that can measure the characteristics of a clock with greater precision. [Solution] The clock modulation circuit of the embodiment includes a clock output circuit, a multiple frequency divider circuit that receives a clock from the clock output circuit and has a plurality of frequency divider circuits that divide the clock, and a frequency divider control circuit that controls the timing of the start of frequency division for each of the plurality of frequency divider circuits and controls the phase difference between at least one pair of output signals of the plurality of frequency divider circuits based on the period of the clock.

The present invention discloses a circuit for generating a multi-phase serial data sampling clock signal, which belongs to the technical field of frequency division circuits, and includes a four-phase clock signal generating circuit for generating a first-phase clock signal, a second-phase clock signal, a third-phase clock signal and a fourth-phase clock signal; a first four-to-one selector, the input end of which respectively inputs the first-phase clock signal, the second-phase clock signal, the third-phase clock signal and the fourth-phase clock signal, the control end respectively inputs the first control signal and the second control signal, and the output end outputs the first clock signal; a two-to-one selector; a first sampling circuit; a second sampling circuit; a third sampling circuit; a fourth sampling circuit; a fifth sampling circuit; a sixth sampling circuit; a second four-to-one selector; a first four-frequency division circuit; and a second four-frequency division circuit. The present invention has a simple structure, uses fewer signals, is more convenient to implement logic circuits, has lower power consumption, and requires a smaller layout area, which can reduce costs.

The utility model provides a frequency divider, a multimode frequency divider, a phase-locked loop circuit, a chip and electronic equipment. The frequency divider comprises a first latch, a second latch, a third latch and a fourth latch which are in feedback cascade connection, the first AND logic circuit is respectively connected with the first latch, the second latch and the fourth latch; the second AND logic is connected between the second latch and the third latch; the third AND logic circuit is connected between the third latch and the fourth latch; and a delay circuit connected with the output end of the second latch, wherein the frequency divider generates an output frequency-divided clock signal through the delay circuit. According to the scheme of the invention, the structure of the frequency divider is optimized, so that the output delay time of the first-stage frequency division module in the multi-modulus frequency divider during signal output is improved, the situation that the signals are sampled by mistake in the subsequent sampling and frequency division process of the frequency division modules is avoided, and the problem that the frequency division ratio is wrong under continuous frequency division change is solved.

A photonic counter circuit presented herein includes a first photonic circuit coupled to a second photonic circuit. A first input of the first photonic circuit is coupled to an output of the first photonic circuit, and a second input of the first photonic circuit receives a photonic clock signal. The first photonic circuit generates a first photonic output bit signal based in part on the photonic clock signal. A first input of the second photonic gate is coupled to an output of the second photonic gate. A second input of the second photonic gate is coupled to the output of the first photonic gate and receives the first photonic output bit signal. The second photonic circuit generates a second photonic output bit signal based in part on the first photonic output bit signal.

The present application provides a clock phase control circuit and a clock phase control method. The clock phase control circuit comprises a frequency divider, a multiplexer and a controller. The frequency divider receives a first clock signal and outputs a plurality of second clock signals. The multiplexer receives the plurality of second clock signals and outputs one of the plurality of second clock signals. The controller is coupled to the frequency divider and the multiplexer. When the controller receives an interrupt signal, the controller outputs a selection signal to the multiplexer according to the interrupt signal. The multiplexer outputs another one of the plurality of second clock signals according to the selection signal. The clock phase control circuit and the clock phase control method of the present application can switch the clock signal appropriately to output a clock signal with appropriate clock frequency.

The invention relates to a semiconductor device, a method for controlling the semiconductor device, and a control program. A semiconductor device according to the present disclosure includes: a comparator circuit; a counter circuit; and a latch circuit that stores a count value of the counter circuit at a timing when an output signal of the comparator circuit changes, the counter circuit including: a multi-phase signal generator; and a plurality of flip-flop circuits including a first-stage flip-flop, a second-stage flip-flop, and a subsequent flip-flop, the first-stage flip-flop receiving an inverted signal of an output signal of the flip-flop in the last stage; and each of the second stage flip-flop and the subsequent flip-flop receives an output signal of the flip-flop in the preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits is output as a count signal of a count value.

An apparatus includes a counter having a clock input, a count value input, a third input, and an output. A multiplexer has a first input, a second input, a selection input, and an output. A delay circuit has a first input coupled to the clock input of the counter, a second input coupled to the output of the counter, a first output and a second output. The first output is coupled to the first input of the multiplexer, and the second output is coupled to the second input of the multiplexer. A fractional control circuit has a first output coupled to the selection input of the multiplexer and has a second output coupled to the third input of the counter.