56 results about "C-element" patented technology

A duty correction circuit includes: a C-element including a first input and a second input; and an inverter connected to the second input of the C-element, wherein the C-element obtains an output of a logic “1” when both inputs are the logic “1”, obtains an output of a logic “0” when both inputs are the logic “0”, and maintains the output to a previous state in other conditions, and complementary clocks having a phase difference of an approximately half cycle are inputted to the first input of the C-element and the inverter respectively.

An LDPC decoding method and apparatus of LDPC decoding a codeword formed by c code bits transmitted through a channel include receiving the codeword and a p x c parity check matrix formed of 0 and 1 values, comparing the codeword with each of p rows of the parity check matrix, the rows formed with c elements, generating an R matrix by obtaining a first minimum value that is a minimum value among elements that are not 0 in each row, a second minimum value that is a second smallest value in the same row, and a location of the first minimum value, and outputting a decoded codeword formed by c code bits by determining one code bit by adding elements of each column of the R matrix.

The invention relates to an electronic device that includes an MCML Muller-c element. The MCML Muller-c element has a first differential stage for operating in a trans- conductance state converting the differential input to a differential output current implementing the logical behavior of the MCML Muller-c element and a second stage operating as a trans-impedance stage being coupled to the first stage. Further, the MCML Muller-c element has peaking circuitry being coupled to the first stage, such that the peaking circuitry and the first stage provide a negative capacitance to the MCML Muller-c element for reducing the damping factor of the MCML Muller-c element.

An RTL hardware description language simulation accelerator and circuit emulator which operates on data driven asynchronous completion handshaking principles. Deploying Muller C elements to control latches, the system does not depend on externally provided clocks or internal timing circuits with delay logic or clock generators. Each levelized domain of logic signals a successor level to begin execution of instructions with a level complete message produced when all its input operands have produced a completion message. Each predecessor stage holds back data production until the successor stage is ready. Each levelized data-driven asynchronous domain evaluation processor is self-timed receiving completion messages from its predecessors, and sending completion messages to its successors.

The invention discloses a light-emitting diode, and belongs to the technical field of photoelectron manufacturing. The light-emitting diode comprises a substrate, a buffer layer, a distribution Prague reflection mirror, an n type limiting layer, an active layer, a p type limiting layer, a GaP window layer and a p type ohmic contact layer which are overlapped in sequence. An n type ohmic contact electrode is arranged on the face, opposite to the buffer layer, of the substrate. A p face bonding wire electrode is arranged on the face, opposite to the GaP window layer, of the p type ohmic contact layer. C element heavily-doped GaP layers overlap between the GaP window layer and the p type ohmic contact layer. The p type ohmic contact layer is an indium tin oxide film. The p face bonding wire electrode is an Al electrode. The p type ohmic contact layer is made of high-transmittance conducting film indium tin oxide instead of Au / AuBe / Au, the electrode mainly made of metal AL is adopted as the p face bonding wire electrode, and therefore the gold consumption in the chip manufacturing process can be greatly lowered, and cost can be effectively and greatly reduced.

An RTL hardware description language simulation accelerator and circuit emulator which operates on data driven asynchronous completion handshaking principles. Deploying Muller C elements to control latches, the system does not depend on externally provided clocks or internal timing circuits with delay logic or clock generators. Each levelized domain of logic signals a successor level to begin execution of instructions with a level complete message produced when all its input operands have produced a completion message. Each predecessor stage holds back data production until the successor stage is ready. Each levelized data-driven asynchronous domain evaluation processor is self-timed receiving completion messages from its predecessors, and sending completion messages to its successors.

A low voltage, low power, wideband quadrature divide-by-three frequency divider using a wideband low voltage, low power differential Muller C element with multiple inputs operates on quadrature input and quadrature output signals. This frequency divider can be used in frequency synthesisers and as quadrature local oscillator generator.

A duty correction circuit includes: a C-element including a first input and a second input; and an inverter connected to the second input of the C-element, wherein the C-element obtains an output of a logic “1” when both inputs are the logic “1”, obtains an output of a logic “0” when both inputs are the logic “0”, and maintains the output to a previous state in other conditions, and complementary clocks having a phase difference of an approximately half cycle are inputted to the first input of the C-element and the inverter respectively.

The asynchronous circuit insensitive to delays comprises at least one time delay insertion circuit on the propagation path of a signal. The delay insertion circuit comprises, between an input and an output of the signal, a Muller C-element and a plurality of delay circuits connected in series to an output of the Muller C-element. The outputs of the delay circuits are connected to corresponding inputs of a multiplexing circuit having an output constituting the output of the delay insertion circuit. The Muller C-element comprises an input connected to the output of the last delay circuit via an inverter gate, and an input constituting the input of the signal to the delay insertion circuit. The multiplexing circuit control circuit preferably comprises a random generator.

Asynchronous nanoelectronic circuits that operate according to principles of quasi-delay insensitive design are described. Circuit or logic elements comprising n-type devices are fabricated in a first n-plane, p-type devices are fabricated in a p-plane, and connections are formed in a routing plane of a compute tile. A state-holding element comprising a selected one of a C-element, a precharge function-block, and a read-write register is described. The state-holding element can hold a value of an output of a logic element during a time when the output is disconnected from a reference voltage. Isochronic forks having an adversary path designed to make state transitions safe are explained.

The present invention relates to an internal antenna for a handset and a design method thereof. The present invention provides an internal antenna for a handset and a design method thereof characterized in that a L / C element is attached to a slot line of an internal anetnna, the attached L / C element is moved along the slot line, or the L / C element having a predetermined inductance / capacitance is attached and detached, thereby easily matching a resonant frequency.

A integrated tested of electric motor car is featured as pre-reserving test ports of three lead out lines of Hall A, B and C elements; Hall element positive electrode power supply; low potential; speed control line of rotary handle; controller master power supply positive electrode; lamp circuit and controller master power supply negative electrode when electric motor car is assembled then inserting said ports into port of said integrated tester for carrying out test on electric motor car.

An antenna module is provided. The antenna module comprises a first radiation conductor, a second radiation conductor, a short-circuit element (s / c element), a ground plane, a feed-in cable and a spurious radiation conductor. One terminal of the second radiation conductor is near the first radiation conductor with a gap. One terminal of the s / c element is connected to the second radiation conductor and the other side of the s / c element is connected to the ground plane. The feed-in cable comprises a centre conductor and an external conductor, wherein the centre conductor is connected to the first radiation conductor and the external conductor is connected to the ground plane. The spurious radiation conductor is connected to the second radiation conductor. The second radiation conductor comprises a spurious radiation plate, a first radiation piece and a second radiation piece within the two sides of the second radiation conductor. The first radiation piece and a second radiation piece are in parallel and a gap is conducted between the first radiation piece and the second radiation piece.