Asynchronous first-in first-out cell

Abstract

The present invention discloses an asynchronous first-in-first-out cell, wherein modified Muller C elements are used to reduce the complexity of the circuit of the asynchronous first-in-first-out cell; the asynchronous first-in-first-out cell of the present invention not only can be reusable, but also can apply to a single-supply-voltage system with a single clock frequency or multiple clock frequencies and a multiple-supply-voltage system with a single clock frequency or multiple clock frequencies. Further, when the asynchronous first-in-first-out cell of the present invention is applied to the interface circuit of a dual-supply-voltage 16-point radix-2² GALS-based FFT architecture, considerable power saving and latency reduction can be achieved.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to an asynchronous first-in-first-out cell, particularly to an asynchronous first-in-first-out cell, which not only can apply to a single-supply-voltage system with a single clock frequency or multiple clock frequencies but also can apply to a multiple-supply-voltage system with a single clock frequency or multiple clock frequencies. [0003] 2. Description of the Related Art [0004] The principle of SOC (System on a Chip) design is to achieve high throughput and low latency. Although the performance of a chip can be promoted via increasing operation frequency, the power consumption of the entire chip system will rise obviously, and a great amount of heat is also generated thereby. Further, owing to the increasing communication time between chip modules, it is hard to distribute a single synchronous clock to the whole chip system. Therefore, a chip system not only needs a power management ...

AI Technical Summary

Benefits of technology

[0007] The primary objective of the present invention is to provide an asynchronous first-in-first-ou...

Problems solved by technology

Although the performance of a chip can be promoted via increasing operation frequency, the power consumption of the entire chip system will rise obviously, and a great amount of heat is also generated thereby.

Further, owing to the increasing communication time between chip modules, it is hard to distribute a single synchronous clock to the whole chip system.

However, the conventional asynchronous FIFO design is implemented w...

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