Asynchronous ping-pong counter

Abstract

An asynchronous ping-pong counter is disclosed. The asynchronous ping-pong counter comprises a first asynchronous counter, a second synchronous counter, and a controller, the asynchronous ping-pong counter operates between a first state and a second state. In the first state, the first asynchronous counter counts a first number of clock edges of a fast clock signal, and the second asynchronous counter holds a first counter output value. In the second state, the second asynchronous counter counts a second number of clock edges of the fast clock signal, and the first asynchronous counter holds a second counter output value. The controller determines a state transition based on a sampling of a slow clock signal by the fast clock signal.

Description

technical field [0001] The invention relates to counter technology, in particular to an asynchronous ping-pong counter (asynchronousping-pong counter). Background technique [0002] In this specification, a counter is defined as a circuit component, which is used to receive a fast clock pulse and a slow clock pulse, and then generate an output value; rising edge (rising edge) is defined as a digital signal digital signal from logic low Level to logic high level conversion process (transition). The output value generated by the counter represents the number of occurrences of the rising edge of the fast clock pulse between two adjacent rising edges of the slow clock pulse. A synchronous counter uses the fast clock as a counting pulse to oversample the slow clock, and determines the number of rising edges of the counting pulse according to the sampling result. [0003] However, assuming that the frequency of the fast clock pulse is very high, such as 5GHz, and the frequency o...

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Problems solved by technology

[0003] However, assuming that the frequency of the fast clock pulse is very high, such as 5GHz, and the frequency of the slow clock pulse is very low, such as 10MHz, it is almost impossible to match every flip-flop ( flip-flop) timing requirements for setup time and hold time

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