The invention discloses a ternary adiabatic JKL flip-flop comprising a ternary adiabatic JKL fundamental circuit and a DTCTGAL buffer, wherein the
signal input end of the ternary adiabatic JKL fundamental circuit is connected with the
signal output end of the DTCTGAL buffer, the
signal output end of the ternary adiabatic JKL fundamental circuit is connected with the signal input end of the DTCTGAL buffer; the complementary signal output end of the ternary adiabatic JKL fundamental circuit is connected with the complementary signal input end of the DTCTGAL buffer; both the ternary adiabatic JKL fundamental circuit and the DTCTGAL buffer are connected with a power
clock signal of an amplitude level corresponding logic 1, a first
clock pulse signal of an amplitude level corresponding logic 2 and a second
clock pulse signal of the amplitude level corresponding logic 2; and the
delay time of the DTCTGAL buffer is the same as that of the ternary adiabatic JKL fundamental circuit, and is half a clock period. The ternary adiabatic JKL flip-flop disclosed by the invention has the advantages that the circuit has very low
power consumption, ternary input and output of the adiabatic circuit are realized while an
energy recovery characteristic is provided, and the circuit has a higher
information density and high
operational reliability.