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Multi-mode programmable frequency divider with 0.5 frequency division step

A technology of frequency divider and step size, which is applied in the direction of asynchronous pulse counter, etc., can solve the problems of power consumption and increase of frequency divider power consumption, and achieve the effect of no glitch, simple circuit structure, and avoid glitch

Inactive Publication Date: 2009-07-15
SOUTHEAST UNIV
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Problems solved by technology

The structure has the characteristics of modularization, which is convenient for layout design, but the added 1 / 1.5 frequency division unit needs to consume 1.5 times the power consumption of the high-speed 2 / 3 frequency division unit
Therefore, the increase of this unit makes the power consumption of the frequency divider increase by about 75% compared with the previous one, which is not suitable for the current trend of low power consumption design

Method used

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  • Multi-mode programmable frequency divider with 0.5 frequency division step
  • Multi-mode programmable frequency divider with 0.5 frequency division step
  • Multi-mode programmable frequency divider with 0.5 frequency division step

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Embodiment Construction

[0014] At present, the high-speed and wide-range programmable frequency divider with integer step size is realized by cascading traditional 2 / 3 frequency division units. The mode control output signal Mo only needs to be fed forward step by step, so it has a strong speed advantage. And it has a very convenient binary frequency division ratio control bit. In order to take advantage of these characteristics of the structure and realize the function of fractional 0.5 frequency division step size, we insert a multiplexer between the first and second stage 2 / 3 units, and realize it by switching signal links of different phases Fractional frequency division step size requirements. The existing frequency divider with a frequency division step of 0.5 mainly adopts a structure based on a frequency division unit of 1 / 1.5 and a technology of sequential phase switching. The former consumes a lot of power, and the latter requires complex circuits to eliminate glitches.

[0015] Such as ...

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Abstract

The present invention discloses a multi- module programmable frequency demultiplier as 0.5 frequency demultiplication step length which comprises 2 / 3 frequency demultiplier unit, multiplex selector and a controller that cascade mutually; a half-adder of n-1 bit used to adjust frequency dividing ratio timely is also included; enable signal C0 of phase switch control module and 2 / 3 unit number setting signal constitute binary system frequency dividing ratio control bit together; output signal can be lead out from any 2 / 3 unit mode control signal output terminal. The fractional step length frequency demultiplier circuit structure of the invention is simple with no bur, increased power consumption is few and flexibility is strong.

Description

technical field [0001] The invention relates to a multi-mode programmable frequency divider with a frequency division step of 0.5, in particular to the technical field of designing a multi-mode programmable frequency divider with high-speed and wide-range fractional frequency division. Background technique [0002] In recent years, with the wide application of delta-sigma fractional frequency synthesizers in radio frequency technology, frequency dividers with fractional frequency division steps have been intensively studied. A large number of studies have shown that every time the frequency division step of the frequency divider is reduced by half, the quantization noise of the modulator can be reduced by 6dB, so that the bandwidth of the frequency synthesizer can be expanded, thereby speeding up the locking speed of the system. In April 2002, the article "A1.5-V900-MHzmonolithic CMOS fast-switching frequency synthesizer for wireless applications" published on pages 459 to 4...

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Application Information

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IPC IPC(8): H03K23/58
Inventor 吴建辉王声扬张萌李红吉新村朱贾峰汤黎明黄福青陈超
Owner SOUTHEAST UNIV
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