High-speed programmable frequency divider

Abstract

The invention relates to a high-speed programmable frequency divider comprising four nand gates and multiple stages of latch combinations. The output end of the first nand gate, the output end of the second nand gate and the output end of the third nand gate are respectively connected with the input end of the fourth nand gate; the first nand gate, the second nand gate and the third nand gate are respectively provided with a control input end; each stage of latch combination comprises a clock high-openness latch and a clock low-openness latch; adjacent latches are connected by a different clock openness latch, namely, the output end of the clock high-openness latch is connected with the input end of the clock low-openness latch, and the output end of the clock low-openness latch is connected with the input end of the clock high-openness latch; the output end of the first stage of clock low-openness latch is connected with the input end of the first nand gate; the output end of the first stage of clock high-openness latch is connected with the input end of the second nand gate; and the output end of the second stage of clock high-openness latch is connected with the input end of the third nand gate.

Description

technical field [0001] The invention relates to frequency divider technology in digital circuits, in particular to a high-speed programmable frequency divider. Background technique [0002] Clock circuits in modern high-speed microprocessors are usually generated by multiplying the input clock frequency with one or more phase-locked loops. An important component of this method of frequency doubling is the frequency divider in the phase-locked loop feedback loop. This crossover needs to be able to handle high frequency signals. Different product performance and the frequency conversion function of the microprocessor generally require that the value of the frequency division ratio can be adjusted. It is also required that the clock phase and duty cycle can be adjusted arbitrarily after frequency division. [0003] There are many types of high-speed frequency dividers to achieve different functional requirements and performance indicators. One type of frequency divider requ...

AI Technical Summary

Problems solved by technology

However, the speed of the frequency divider decreases after the number of stages of the frequency divider increases. At the same time, because the coding structure of the random generator is used to realize the programmable function of frequency division, after the number of stages increases, the logic design of the random code decoder will change very much. complex

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