A three-valued addition counter based on cnfet

Abstract

The invention discloses a three-valued addition counter based on CNFETs. The three-valued addition counter comprises a pulse signal generator, n addition counting units, and an n input AND gate. The pulse signal generator has an input end and output end. Each addition counting unit has an input end, an output end, a clock control end, and a carry output end. The n input AND gate has n input ends and an output end. The output end of the pulse signal generator is connected with the clock control ends of the n addition counting units. The carry output ends of the n addition counting units and the n input ends of the n input AND gate are connected in one-to-one correspondence. The output end of the n input AND gate is the carry output end of the three-valued addition counter. The carry output end of the kth addition counting unit is connected with the input end of the (k+1)th addition counting unit, wherein k=1, 2, ..., n-1. The output end of the jth addition counting unit is the jth output end of the three-valued addition counter, wherein j=1, 2, ..., n. The three-valued addition counter reduces invalid operation, decreases circuit power consumption and time delay, and has a high-speed low-power-consumption characteristic.

Description

technical field

[0001] The invention relates to a three-value addition counter, in particular to a CNFET-based three-value addition counter. Background technique

[0002] With the development of CMOS technology and integrated circuit technology, the miniaturization of circuits brings great convenience to people's lives, and at the same time puts forward higher requirements for characteristics such as high integration and low power consumption. Especially for the issue of high integration, due to the reduction of feature size, the number of integrated components per unit chip area has increased sharply, and the feature size of integrated circuits has entered the nanometer level. In VLSI (Very Large Scale Integration, VLSI), more than 70% of the silicon area is used for wiring, which further restricts the improvement of integration. At the nanometer level, problems such as gate delay, interconnect crosstalk, and power consumption increase caused by interconnect parasitic effe...

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