Multiple-valued counter unit based on nerve MOS tube and multi-digit multiple-valued counter

A MOS tube and counter technology, applied in the field of multi-bit multi-value counters, can solve the problems of high cost, high power consumption, and cumbersome design of counters, and achieve the effect of saving quantity, reducing cost and power consumption

Inactive Publication Date: 2013-07-17
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Traditional four-value counters are mostly implemented by four-value D flip-flops and four-value gate circuits, but these four-value components have complex structures and cumbersome designs, resulting in high cost and high power consumption of the counter, which is not conducive to improving the integration of the circuit

Method used

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  • Multiple-valued counter unit based on nerve MOS tube and multi-digit multiple-valued counter
  • Multiple-valued counter unit based on nerve MOS tube and multi-digit multiple-valued counter
  • Multiple-valued counter unit based on nerve MOS tube and multi-digit multiple-valued counter

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Embodiment 1

[0020] Embodiment 1: A multi-valued counter unit based on neural MOS transistors, comprising a neural MOS source follower 1 and a unit trigger circuit connected to the input control gate of the neural MOS source follower, the unit trigger circuit includes the first A binary D flip-flop 2, a second binary D flip-flop 3, an AND gate 4 and an OR gate 5, the second input terminal C of the first binary D flip-flop 2 0 and the second input C of the second binary D flip-flop 3 1 And connected to the clock signal input terminal CP, the first input terminal D of the first binary D flip-flop 2 0 with the second output of the second binary D flip-flop 3 connection, the first input D of the second binary D flip-flop 3 1 and the first output terminal Q of the first binary D flip-flop 2 0 Connected to the first input end of the OR gate 5 and the second output end of the first binary D flip-flop 2 And the first input terminal of AND gate 4 is connected, and the first output terminal Q ...

Embodiment 2

[0021] Embodiment two: a kind of multi-bit multi-valued counter based on neural MOS tube, including two first multi-valued counter unit 10 and the second multi-valued counter unit 20 connected in series, the clock input of the second multi-valued counter unit 20 The terminal CP2 is connected with the first multi-valued counter unit 10 through an auxiliary AND gate 6, and the first multi-valued counter unit 10 includes a neural MOS source follower 11 and an input control gate connected to the neural MOS source follower. A unit trigger circuit, the unit trigger circuit includes a first binary D flip-flop 21, a second binary D flip-flop 31, an AND gate 41 and an OR gate 51, the second input terminal C of the first binary D flip-flop 21 01 and the second input terminal C of the second binary D flip-flop 31 11 And connected to the clock signal input terminal CP1, the first input terminal D of the first binary D flip-flop 2 01 and the second output terminal of the second binary D f...

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Abstract

The present invention discloses a neuron MOS based multi-valued counter unit. The counter unit includes a neuron MOS source follower and at least a control gate connected the neuron MOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the neuron MOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the neuron MOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption. The present invention applies the asynchronous carry-over concept to implement the multi-digit multi-value counter, and it also has been verified by the simulation of P Simulation Program with Integrated Circuit Emphasis (SPICE).

Description

technical field [0001] The invention relates to a multi-value counter, in particular to a multi-value counter unit and a multi-bit multi-value counter based on neural MOS transistors. Background technique [0002] At present, integrated circuits are developing at a speed exceeding Moore's law, and the scale of circuits that can be integrated on a chip is getting larger and faster. As a result, the power consumption of integrated circuits is increasing. The huge power consumption not only makes various portable devices encounter difficulties in power supply, but also the overheating of chips also makes them prone to work failure and shorten their lifespan. On the other hand, due to the advancement of semiconductor process technology, the area occupied by gate circuits has dropped sharply. On the contrary, in the substrate of VLSI, more than 70% of the silicon area is used for wiring. Therefore, the integration degree of the circuit is limited, the production cost of the inte...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06M1/272H01L29/78
CPCH01L29/42328
Inventor 汪鹏君张跃军
Owner NINGBO UNIV
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