30 results about "Many-valued logic" patented technology

Circuit structure and resulting circuitry for multiple-valued logic. The circuit structure allows the design and fabrication of any r-valued logic function of n-places where r is an integer greater than 1 and n is an integer greater than 0. This structure is called SUpplementary Symmetrical LOgic Circuit structure (SUS-LOC). In circuits incorporating SUS-LOC, circuit branches are realized that uniquely deliver circuit response and output. For some circuits, and due to the operating characteristics of the switch elements, additional circuit elements, or stages, must be incorporated to prevent "back biasing." SUS-LOC is fully active. Only active elements perform logic synthesis and those components not directly related to logic synthesis, such as resistors and/or other passive loads, are relegated the task of circuit protection. The fabrication of r-valued, multi-valued, or multiple-valued logic circuits, designed using the definitions of the SUS-LOC structure can be accomplished with known techniques, materials, and equipment.

An IC solution utilizing mixed FPGA and MLC arrays is proposed. The process technology is based on the Schottky CMOS devices comprising of CMOS transistors, low barrier Schottky barrier diode (SBD), and multi-level cell (MLC) flash transistors. Circuit architectures are based on the pulsed Schottky CMOS Logic (SCL) gate arrays, wherein a variable threshold NMOS transistor may replace the regular switching transistor. During initialization windows, existing FPGA programming techniques can selectively adjust the VT of the switching transistor, re-configure the intra-connections of the simple SCL gates, complete all global interconnections of various units. Embedded hardware arrays, hardwired blocks, soft macro constructs in one chip, and protocols implementations are parsed. A wide range of circuit applications involving generic IO and logic function generation, ESD and latch up protections, and hot well biasing schemes are presented. The variable threshold transistors thus serve 3 distinctive functions. It acts as an analog device to store directly nonvolatile information in SCL gates. It couples the diode tree logic functions. Finally, it stores and operates large amount of information efficiently. The mixed SCL type FPGA and MLC storages shall emerge as the most compact logic and memory arrays in Si technology. Low power, high performance, and high capacity ICs are designed to mix and replace conventional CMOS-TTL circuits. The idea of multi-value logic composed of binary, ternary, and quaternary hardware and firmware is also introduced.

The invention discloses a memristor-based nonvolatile multivalued logic device and an operating method thereof. The method provides an operating method for negation and dextrorotation of three-valued logic and multivalued T gate logic, which realizes an exhaustive set of multivalued logic, such as three-valued logic based on the multi-resistance state transition characteristic of a memristor. All the logic operation results are stored in the device in a nonvolatile resistance state, such that a logic operation function and a data storage function are realized simultaneously in the device, i.e., storage and calculation are fused; therefore, a device basis is laid for going beyond the limitation from an information device Moore's law and breaking through the Von Neumann bottleneck in a computer architecture. The memristor-based multivalued logic device disclosed by the invention can be applied to a novel solid-state memory, a logic-arithmetic unit, a programmable gate array, an on-chip system and other fields as a basic unit, and provides a new path for boosting novel computer architecture.

Predicting data correlation using multivalued logical outputs in SRAM storage cells including generating a plurality of logical outputs for each of a plurality of variable sets, wherein each variable in each variable set is a data point, and wherein each logical output is a binary indication of a relationship between the data points; writing, into storage cells, each logical output of the plurality of logical outputs for each of the plurality of variable sets; and for each group of corresponding logical outputs of the plurality of logical outputs: activating a fight port for the storage cells storing corresponding logical outputs, wherein activating the fight port causes each corresponding logical output to adjust a resulting voltage based on the logical output stored in each storage cell; and measuring the resulting voltage on a bitline of the activated fight port to determine a correlation probability for the corresponding logical outputs.

The invention discloses a multiple-valued counter unit based on an MOS tube, which comprises a nerve MOS source electrode follower and at least one unit trigger circuit connected on an input control grid of the nerve MOS source electrode follower, wherein the unit trigger circuit comprises a first binary D flip-flop, a second binary D flip-flop, an And gate and an OR gate. The invention has the advantages that the nerve MOS tube is used to substitute for complex threshold operation in multi-valued logic, thereby realizing multi-valued logic on the true sense, the multi-valued counter with different cardinal numbers can be realized by increasing the number of the unit trigger circuit forming the binary D flip-flops and connecting the unit trigger circuit forming the binary D flip-flops with an idle input control grid of the source electrode follower. Compare with the traditional multi-valued counter, the invention can greatly save the number of the components, and reduce the cost and the energy consumption of circuit design. The invention adopts the mode of asynchronous carry to realize the multi-digit multi-valued counter on the basis of the multi-valued counter unit, and the circuit which is designed by using PSPICE simulation verification has correct logical function.

The invention discloses a twin-storage type multi-valued physically unclonable functional circuit which comprises a time sequence control circuit, a decoder, a driver, a pre-charge circuit, a PUF (physically unclonable function) array, 16 data loading circuits and 16 interface circuits. The driver comprises 32 driving circuits with identical structures, and 512 PUF circuits are arranged accordingto a 32 row*16 column mode to form the PUF array. The twin-storage type multi-valued physically unclonable functional circuit has the advantages that 2-bit random source data can be generated by the PUF circuits which are of twin structures, four-valued data can be outputted by multi-valued logic circuits formed by the data loading circuits and the interface circuits, and accordingly the quantities of bit lines can be reduced by 50%; the twin-storage type multi-valued physically unclonable functional circuit is designed in full-custom modes by the aid of TSMC_LP65nm processes, and the area ofthe twin-storage type multi-valued physically unclonable functional circuit is 0.019 mm<2>; as shown by test results, the lowermost work voltages of the twin-storage type multi-valued physically unclonable functional circuit are 320 mV, corresponding work frequencies are 110 kHz, the hardware utilization rate is increased by 15% at least, and energy consumption is reduced by 30%.

Method and apparatus for providing a hidden signature to a recording medium, such as an optical disc (102). The hidden signature is generated in relation to the selected sequencing of data blocks (132, 134, 136, 138, 140, 142). A plurality of) mutually exclusive, valid possible states are identified for each of the data blocks (202), each state conforming to requirements set forth by a published standards document to which the optical disc conforms. A different logical value is assigned to each of the possible states, and the hidden signature is selected as a multi-value logical word comprising a sequence of the logical values (204). The hidden signature is thereafter written to the optical disc by writing a set of corresponding data blocks at selected locations on the optical disc having states corresponding to the multi-value logical word (206). The hidden signature thereafter facilitates copy protection or forensic tracking efforts (208).

The invention discloses a three-valued thermal-insulation domino direct circulation valve and a three-valued thermal-insulation domino reverse circulation valve which respectively comprise a three-valued low-power dissipation domino JKL trigger, wherein each three-valued low-power dissipation domino JKL trigger consists of a first three-valued thermal-insulation domino text calculation circuit, a second three-valued thermal-insulation domino text calculation circuit, a third three-valued thermal-insulation domino text calculation circuit, a fourth three-valued thermal-insulation domino text calculation circuit and a basic three-valued JKL trigger circuit; thermal-insulation logic, multi-valued logic and multi-domino circuits are combined together through the first to fourth three-valued thermal-insulation domino text calculation circuits, thus realizing a three-valued low-power dissipation domino JKL trigger; and the three-valued thermal-insulation domino direct circulation valve and the three-valued thermal-insulation domino reverse circulation valve have the advantages of being high in circuit integration and information density and low in power dissipation on the basis of the three-valued low-power dissipation domino JKL trigger.

The invention relates to an address decoding method based on a multi-valued logic circuit, in particular relates to an address decoding method for accessing a plurality of storage units once, and belongs to the technical field of digit circuits. The method is characterized in that 2n AND gates are adopted, and the created address decoding method is provided with 2n input ends; 2n address signals of storage units to be selected are respectively sent to the 2n input ends of the address decoding method; the 2n AND gates of the address decoding method are respectively subjected to AND operation; the corresponding storage unit can be selected as result is equal to 1, and thus the corresponding read and write circuit can be driven. The method has the advantages that multi-valued addressing is realized, the storage data can be read and written at the same time, the novel storage or processing devices apply, and parallel processing of data is supported.

The invention discloses a three-value low power consumption domino JKL trigger. The three-value low power consumption domino JKL trigger consists of a first three-value heat-insulating domino character operational circuit, a second three-value heat-insulating domino character operational circuit, a third three-value heat-insulating domino character operational circuit, a fourth three-value heat-insulating domino character operational circuit and a three-value JKL trigger basic circuit, wherein a heat-insulating logic, a multi-value logic and a domino circuit are combined together by the first three-value heat-insulating domino character operational circuit, the second three-value heat-insulating domino character operational circuit, the third three-value heat-insulating domino character operational circuit and the fourth three-value heat-insulating domino character operational circuit. The three-value low power consumption domino JKL trigger has the advantages that the circuit integration level and information density of the JKL trigger are improved; and compared with a conventional three-value domino JKL trigger, the three-value low power consumption domino JKL trigger disclosed by the invention has the characteristic that energy consumption is saved by 69 percent.

The invention discloses a method for generating a bit operation test case based on four-valued logic, and belongs to the technical field of test case generation in a software test. The method specifically comprises the following steps: a first step of setting a four-valued logic operation method and an inverse operation method of four-valued logic operation; a second step of resolving a bit operation constraint into logic operation constraints; a third step of enabling the logic operation constraints to correspond to constraint satisfaction problems; a fourth step of solving the logic operation constraints by virtue of a search algorithm according to the four-valued logic operation and inverse operation methods; and 5 synthesizing the solutions of the logic operation constraints into a solution of the bit operation constraint. The method has the advantages that the range of a variable is computed by employing the multi-valued logic, so that the search efficiency of the search space and the bit operation is improved; and the test case generation efficiency of the bit operation is further improved.

Provided are a data transmission apparatus and method for transmitting data in a Delay-Insensitive (DI) data transmission method supporting a handshake protocol. The data transmission apparatus includes a sender which outputs a binary-valued logic signal based on binary-valued logic, and an encoder which encodes the binary-valued logic signal input through input wires into a multi-valued logic signal based on multi-valued logic and transmits the encoded multi-valued logic signal to a decoder through output wires. Here, the encoder includes a mapping table which stores input variables including the number of input wires and the number of output wires smaller than the number of input wires and the multi-valued logic signal corresponding to the input variables, and encodes the binary-valued logic signal into the multi-valued logic signal with reference to the mapping table.

A hardware security unit and a multiple-valued logic operational method thereof are provided, which comprises at least a first and a second multiple-valued logic calculation units, an operational unit, a judgment unit and an execution unit. The first multiple-valued logic calculation unit and the second multiple-valued logic calculation unit are connected to the operational unit, each of the multiple-valued logic calculation units comprises at least three registers for describing expected logical state, current logical state and a multiple-valued logic operator of a specific entity of the hardware security unit. The operational unit calculates the expected logical states of the first and second multiple-valued logic calculation units and the current logical states of the first and second multiple-valued logic calculation units, respectively, by using the multiple-valued logic operator in the third register of the second multiple-valued logic calculation unit, so as to obtain expected and current logic operation results. The judgment unit is connected to the operational unit, for judging whether the current logic operation result has reached the expected logic operation result. The execution unit is connected to the judgment unit, for executing a corresponding operation based on the judgment result by the judgment unit. When it is determined that the current logic operation result equals to the expect logic operation result, the hardware security unit performs a corresponding operation. Therefore, a hardware security unit and a multiple-valued logic operational method thereof are provided for solving the problems arise upon providing services to the overall trust chain based on a binary logic judgment.