Differential power analysis defense adder employing sense amplifier based logic

Abstract

The invention discloses a differential power analysis defense adder employing sense amplifier based logic. The adder consists of four two-input not and / and gates, eight two-input exclusive or / nor gates, twenty-two inverters and a carry look-ahead generation circuit. The adder has the advantages that a TSMC 65nm CMOS technology is adopted; simulation analysis is performed on the circuit by a Spectre tool; an experimental result indicates that the adder has a correct logic function; compared with the traditional adder circuit, the adder has the advantage that the power independence can be improved by 97%; and differential power analysis can be effectively defended.

Description

technical field [0001] The invention relates to an adder, in particular to a defensive differential power analysis adder utilizing sensitive amplification logic. Background technique [0002] With the development of integrated circuits and computer technology, cryptographic devices are widely used in smart cards, e-commerce and other fields, which greatly guarantee the security of the system. However, when cryptographic devices process different data, physical information such as energy consumption, running time, and electromagnetic radiation has a certain correlation with the processed data. Therefore, attackers usually use these physical information to attack cryptographic devices to obtain key information, and this method is called Side Channel Attack (SCA). Among a series of side-channel attack techniques, Differential Power Analysis (DPA) technology is a common and effective side-channel attack method, which seriously threatens the security of cryptographic devices. I...

AI Technical Summary

Problems solved by technology

Compared with SABL, TDPL balances power consumption by introducing an additional discharge stage, which increases its energy consumption. If the attacker modifies the clock to generate a separate discharge stage power consumption, the TDPL anti-DPA attack performance will be greatly reduced; ADDL timing control is complex, and When interacting with CMOS circuits, complex interface circuits need to be designed

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