Tri-valued, thermal-insulating and low-power multiplier unit and multiplier

Abstract

The invention discloses a tri-valued, thermal-insulating and low-power multiplier unit and a multiplier. The multiplier unit controls each NMOS tube in an input signal sampling circuit to sample input signals by using a clock-controlled clock signal; four corresponding integrating circuit modules and carry output circuits with cross storage-type structures are constructed by sampled values according to required realized multiplication logic relationship through the bootstrap operation of the NMOS tube; power clocks phi1 and phi complete the evaluation and energy recovery of the output load torealize correct logic function; and compared with a DPL tri-valued multiplier, the four-digit tri-valued thermal-insulating and low-power multiplier can save energy consumption by about 91 percent in0.9 microsecond and has distinct low-power characteristics.

Description

technical field [0001] The invention relates to a multiplier, in particular to a ternary adiabatic low power consumption multiplier unit and a multiplier. Background technique [0002] Multiplication is a basic operation in digital signal processing. In digital signal processing such as images and voices, the multiplier plays an important role and largely affects the power consumption of the system. For example, the power consumed by the multiplier usually accounts for the entire DSP (Digital Signal Processing, digital signal Processing) about 50% of chip power consumption. Most of the traditional CMOS integrated circuits are powered by DC power supply, and its energy is always consumed by power supply→capacitance→ground at one time, although it can be reduced by reducing the power supply voltage and node capacitance, reducing switch redundancy jumps, etc. power consumption, but its power savings are very limited. However, "Design of adiabatic 4-2 compressor and multiplie...

AI Technical Summary

Problems solved by technology

However, most of the traditional multi-valued logic (such as three-valued multiplier unit) circuits adopt gate-level design technology, that is, the gate circuit is the smallest structural unit, the circuit structure is complex, and the power consumption is high.

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