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Ternary adiabatic domino multiplication unit

A multiplication unit, domino technology, applied in instruments, electrical digital data processing, digital data processing components and other directions, can solve problems such as waste

Active Publication Date: 2013-01-30
NINGBO UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the traditional multiplication unit is a huge waste because the charge is consumed from the power supply to the ground at one time; while the adiabatic multiplication unit using an AC pulse power supply can fully recover the charges stored in the circuit nodes and effectively reduce the power of the circuit. consumption

Method used

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  • Ternary adiabatic domino multiplication unit

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Embodiment

[0032] Embodiment: a three-value adiabatic domino multiplication unit, comprising a first three-value adiabatic domino word operation circuit, a second three-value adiabatic domino word operation circuit, a carry signal generating circuit and a local product signal generating circuit; the first three-value adiabatic domino The word operation circuit includes a word operation module and a waveform conversion module. As shown in Figure 2(a), the word operation module consists of a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a sixth PMOS transistor P6, and a third PMOS transistor P3. An NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6 and a seventh NMOS transistor N7, the gate of the first NMOS transistor N1 It is connected in parallel with the gate of the fourth NMOS transis...

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Abstract

The invention discloses a ternary adiabatic domino multiplication unit. The unit comprises a first ternary adiabatic domino literal arithmetic circuit, a second ternary adiabatic domino literal arithmetic circuit, a carry signal generating circuit and a standard product signal generating circuit, wherein the first ternary adiabatic domino literal arithmetic circuit is connected with the carry signal generating circuit and the standard product signal generating circuit respectively, the second ternary adiabatic domino literal arithmetic circuit is connected with the carry signal generating circuit and the standard product signal generating circuit respectively, and the low order carry signal input end of the carry signal generating circuit is connected with the low order carry signal input end of the standard product signal generating circuit. The unit has the advantages that the structure is simple under the guarantee of the correct logic function, compared with the conventional ternary domino multiplication unit in which a direct current power supply is adopted, the power consumption of the unit is saved by about 54%, and compared with a ternary multiplication unit based on design of a double power clock ternary clocked transmission gate adiabatic logic (DTCTGAL) circuit, the amount of transistors is reduced by about 31%.

Description

technical field [0001] The invention relates to a multiplication unit, in particular to a three-value adiabatic domino multiplication unit. Background technique [0002] The current digital circuit system is mainly implemented by binary logic, and the logic values ​​that can be transmitted by a single signal line are only 0 and 1, and the space and time utilization ratio of the circuit is low. The use of multi-valued logic can greatly reduce the number of circuit input variables and increase the amount of information carried by each connection, thereby reducing the area of ​​the chip and enhancing the data processing capability. Due to its advantages in circuit area and speed, domino circuits are widely used in various high-performance circuits. Therefore, the combination of multi-valued logic and domino circuits can further reduce the circuit area and improve the information density of the circuit. [0003] Multipliers are one of the key components of modern digital system...

Claims

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Application Information

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IPC IPC(8): G06F7/523
Inventor 汪鹏君杨乾坤郑雪松
Owner NINGBO UNIV
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