121 results about "Hardware emulation" patented technology

The invention discloses a chip design method, system and device based on a multi-core heterogeneous architecture and a medium. The method comprises the steps that the type and number of heterogeneous computing cores are determined according to a target application scene, and a task scheduling unit is configured; designing an on-chip interconnection structure of a heterogeneous computing core by adopting a hybrid topological structure, and verifying and adjusting a dynamic task scheduling strategy and the on-chip interconnection structure through hardware simulation; configuring a power management unit according to the energy efficiency optimization target, wherein the power management unit is used for controlling the working state of the heterogeneous computing core; operating data of the heterogeneous computing core are collected in the post-silicon verification stage, a firmware updating scheme is generated according to the operating data, and firmware updating is conducted according to the firmware updating scheme. By optimizing the chip design process under the multi-core heterogeneous architecture, the performance, the energy efficiency ratio and the reliability of the chip are improved, and the method can be widely applied to the technical field of chip design.

A hardware emulator and an emulation system including the hardware emulator are provided. The hardware emulator includes an artificial neural network-based reconstruction model configured to reconstruct dynamics of a dynamical system based on input data and a memristor-based circuit configured to emulate state space representation of the dynamical system based on the reconstruction model.

The invention discloses a hardware simulation platform environment anomaly detection method based on dynamic hierarchical clustering. The method comprises the following steps: S1, forming a standardized feature vector data stream; s2, constructing a multi-dimensional feature vector set reflecting the environment state of the hardware simulation platform according to the standardized feature vector data stream; s3, generating an initial clustering center and an initial hierarchical division structure; s4, updating the hierarchical structure, the clustering center and the classification standard of the initial hierarchical clustering model in real time; s5, on the basis of the hierarchical clustering model updated in real time, calculating the deviation degree between each feature vector and the clustering center to which the feature vector belongs, and carrying out anomaly judgment on the feature vectors of which the deviation degree exceeds a preset threshold value, so as to realize the recognition of the abnormal environment data of the hardware simulation platform; and S6, generating an abnormal alarm signal for the identified abnormal data. According to the invention, slight anomalies and serious anomalies can be effectively distinguished, and the anomaly detection precision is improved.

The invention provides an artificial intelligence chip pre-silicon verification system and method, and relates to the technical field of artificial intelligence chips, and the system comprises a model importing layer which is used for importing a current model; the model analysis layer is used for analyzing the current model to obtain a calculation graph; the distributed strategy configuration layer is used for configuring a distributed topology strategy of a hardware simulator of the artificial intelligence chip based on the distributed strategy of the current model, and adjusting a computational graph of the current model to enable the computational graph to be matched with the distributed topology strategy; the performance prediction layer is used for determining the operation performance data of the current model in the artificial intelligence chip based on the operation performance data of each operator; or determining a performance prediction result of the current model in the artificial intelligence chip based on the performance prediction result of each operator; and the operator implementation layer is used for controlling the hardware simulator to run each operator in the computational graph. According to the system and the method provided by the invention, the end-to-end whole-process verification from model input to result output is carried out on the artificial intelligence chip.

The embodiment of the invention provides a hardware verification method and device, electronic equipment and a storage medium, and relates to the technical field of hardware verification. The method comprises the following steps: dividing a time slice into an execution time slice of a software test tool and an execution time slice of a hardware simulator; writing simulation input data into the hardware simulator through a data interface of the hardware simulator after all events which can be executed at the current moment in the software test tool are executed in the execution time slice of the software test tool; converting the time slice into an execution time slice of a hardware simulator, calling a control interface of the hardware simulator in a software environment, and controlling the hardware simulator to operate so as to perform hardware verification; and converting the time slice into an execution time slice of a software test tool, and obtaining a hardware verification result through a data interface of the hardware simulator. Event manager data of software and hardware are synchronized through the data interface, and hardware verification in a software environment by using a software test tool is supported.

The invention relates to a software and hardware co-simulation chip verification method, system and device and a storage medium, and relates to the field of software and hardware co-simulation. The method is based on a hyperSemu system comprising an hsComple and an hsRun and an FPGA (Field Programmable Gate Array) comprising a DUT (Device Under Test) and a Transactor. The method comprises the following steps of: writing an RTL (Real Time Language) design code of a chip; compiling the RTL design code by utilizing hsCompile to obtain a DB file; downloading the DB file to an FPGA (Field Programmable Gate Array) through hsRun so as to carry out hardware simulation; according to the DUT and the Transactor, a Hybrid server program and a Hybrid client program are written, and the Hybrid client program comprises a simulator program and a Linux system; and performing software simulation in the Linux system according to the DUT and the simulator program. The technical effect of the invention is that the efficiency and speed of chip simulation verification are improved.

The invention provides a universal serial bus (USB) 2.0 host speed reduction bridge based on bidirectional protocol handshake and a prototype verification or hardware simulation acceleration platform, which are characterized in that a slow-speed side module runs at a slow clock frequency, is responsible for realizing a protocol layer of a USB protocol and a physical link layer function of the USB protocol, and communicates with a USB2.0 host controller in a chip design (DUT) to be tested; the original speed side module works under the original clock frequency, logic of a protocol layer of a USB protocol and a physical link layer of the USB protocol is achieved, communication with an external real USB2.0 slave end device is achieved through a USB2.0 PHY, data caching and synchronization are achieved through a data caching RAM, and the bridge control module overall plans the whole situation and accurately regulates and controls independent handshake of the USB2.0 protocol layers on the two sides under the original clock frequency. Through bidirectional protocol handshake on the two sides of the speed reduction bridge, data communication between a low-speed to-be-tested chip design (DUT) in a chip prototype verification platform and external standard-speed real USB slave equipment is achieved through the speed reduction bridge.

The invention relates to a hardware simulation accelerator multi-user access method, system and device and a storage medium, and is applied to the technical field of hardware simulation accelerators, and the method comprises the following steps: distributing a plurality of resource blocks for different users in a hardware simulation accelerator to obtain a user resource block corresponding table; virtualizing the plurality of PCIe devices in the host interface card to obtain a plurality of mutually independent virtual function devices; constructing a plurality of device driving programs corresponding to the plurality of virtual function devices in the host server; binding a plurality of corresponding equipment driving programs for different users in the host server to obtain equipment driving program binding information; and performing multi-user access of the hardware simulation accelerator according to the user resource block corresponding table, the device driver binding information and the plurality of virtual function devices. The method has the technical effect that the multi-user access to the hardware simulation accelerator can be realized faster and more stably.

The invention relates to the technical field of chips, and provides a coverage rate analysis method for chip verification and a related device. The method is applied to hardware simulation equipment in which simulation codes are stored, the simulation codes comprise RTL codes used for simulating a chip and target codes used for simulating a recorder, and the chip comprises a controller and a memory; the method comprises the steps that in the process that a controller conducts chip verification through a preset test case, a recorder monitors a plurality of preset key signals; when the recorder monitors that any key signal is triggered, a test result corresponding to the key signal is stored in a storage area of the recorder; wherein the storage area and the memory have a mapping relationship; and the controller accesses the memory according to the mapping relation to obtain a test result set of the test cases in the storage area and performs coverage rate analysis. Therefore, the coverage rate information is obtained in real time in the chip verification process, and the efficiency and accuracy of coverage rate analysis are improved.

The invention discloses a software and hardware co-simulation field recovery method and device, equipment and a medium. Comprising the steps of defining a recording starting point and a storage time point of a simulation site; from the recording starting point to the storage time point, capturing transaction flow and causal metadata from the hardware simulation environment of the simulation site to the software test platform, and meanwhile, storing a state snapshot of the verified design in the hardware simulation environment; and when a recovery instruction is received, performing simulation field recovery based on the transaction flow, the causal metadata and the state snapshot. By defining the time range of data capture, a clear boundary is delimited for subsequent data storage, and pertinence and integrity of data records are ensured. A basis is provided for semantic reconstruction of a software test platform by capturing a transaction flow and causal metadata, a state snapshot ensures that the verified design hardware state can be accurately restored, and complete storage of recovery data on the two sides of software and hardware is achieved. And the system does not need to be restarted from the starting point during recovery, so that a redundancy initialization process is avoided, and the simulation debugging efficiency is improved.

The invention provides a low-power-consumption simulation method and device, equipment, a storage medium and a program product, and relates to the technical field of integrated circuits. The method comprises the following steps: determining an initial comprehensive model of a register transfer level corresponding to a to-be-simulated chip; based on the initial comprehensive model, determining a target comprehensive model corresponding to the to-be-simulated chip; according to the initial gate-level netlist corresponding to the to-be-simulated chip, generating a target gate-level netlist corresponding to a power supply loop in low-power-consumption simulation; and based on a preset hardware simulation accelerator, performing low-power-consumption simulation including a power supply loop on the target synthesizable model and the target gate-level netlist. According to the method, the low-power-consumption simulation convergence time is greatly shortened, and the simulation efficiency is improved.

The embodiment of the invention provides a verification method and device, electronic equipment and a storage medium, and the method comprises the steps: dividing a to-be-verified code file into a first code file and a second code file based on a module time sequence requirement corresponding to each module in the to-be-verified code file; the module time sequence requirement of the first module contained in the first code file is lower than the module time sequence requirement of the second module contained in the second code file; compiling the first code file into an executable file, and performing software simulation verification in a software simulation environment based on the executable file; deploying a target bit file corresponding to the second code file to a specified chip, and performing hardware simulation verification in a hardware simulation environment based on the specified chip; and the software simulation environment and the hardware simulation environment perform bidirectional data synchronization based on the target communication interface. A software and hardware combined verification mode is adopted, the verification effect is improved, the verification advantages of the two verification modes are considered at the same time, and the method has the advantages of being convenient to debug and high in verification precision.

A method includes receiving, by a processing device, receiving a data file, dividing the data file into a plurality of partitions based on a defined criteria, compiling the plurality of partitions associated with the data file to form a plurality of compiled partitions, generating a status identifier for each of the plurality of partitions, wherein the status identifier reflects a current version of a corresponding partition. The method further includes combining the plurality of compiled partitions to form a first executable file, and storing the plurality of compiled partitions and a corresponding status identifier for each of the plurality of compiled partitions in a first storage area of a first storage medium. The method also includes receiving a request for the data file, identifying that one or more partitions of the plurality of partitions is reusable, and sending the one or more partitions identified as being reusable.

The invention provides a front-end and back-end simulation implementation system with an RDMA network card, and the system comprises a front-end QEMU simulator which is used for simulating a front-end part of the RDMA network card; the back-end QEMU simulator is used for simulating the back-end part of the RDMA network card; the APP component is used for simulating an RDMA message processing engine and simulating and realizing an RDMA message processing process, and at least comprises the steps of analyzing a hardware table item, constructing a sending message, processing a receiving message and updating a completion queue; and data interaction among the front-end QEMU simulator, the rear-end QEMU simulator and the APP component is realized through a Socket mechanism, so that a simulation process of a control plane data stream and a data plane data stream of the RDMA network card is realized. The invention further discloses a corresponding method, equipment and a storage medium. By implementing the method, the resource cost of real hardware simulation can be reduced, and the chip design verification cost is greatly saved.

The invention relates to an embedded chip simulation and debugging method and system. The method comprises the following steps: expanding an instruction decoding module, a register description module and a breakpoint management module which support a C28x instruction set in a GDB debugger, and generating a special debugging front-end program; the method comprises the following steps: expanding a C28x JTAG protocol adaptation module in an OpenOCD debugging agent, and generating a debugging agent program; a C28x instruction set execution simulation unit is realized in the NEMU simulator, and a GDB Server communication module is embedded in the NEMU simulator; seamless switching between a simulation debugging mode and a hardware debugging mode is realized based on a unified configuration file through a software and hardware debugging environment rapid switching control module. The problems that a traditional debugging mode depends on a special hardware simulator, the cost is high and the simulation environment is inaccurate are solved, and through an integrated software and hardware collaborative debugging scheme, the debugging cost is greatly reduced, and the development efficiency and the comprehensiveness of system verification are improved.

The invention provides an automatic driving formation hardware-in-the-loop simulation platform based on a satellite position simulation platform and a medium, and relates to the technical field of automatic driving and car networking simulation. The platform comprises a satellite position simulation module, a traffic simulation platform, a hardware verification platform, a simulation bus and a clock synchronization module. The satellite position simulation module generates satellite data with a timestamp; the traffic simulation platform constructs a formation driving scene and operates a formation control algorithm; the hardware verification platform comprises a real phased-array antenna module and a PC5 communication device. The modules exchange data through a simulation bus, and the clock synchronization module unifies the time reference to form a closed-loop verification environment of simulation hardware simulation. The problems that space-based data and ground simulation are separated and real communication characteristics are difficult to quantitatively evaluate in the prior art are solved, the satellite-ground cooperation and formation control strategy can be efficiently and reliably verified in a laboratory environment, and the real vehicle test cost and risk are remarkably reduced.

The invention relates to the technical field of chip design simulation verification, in particular to a memory type dynamic determination method for prototype verification and hardware simulation, and the method comprises the steps: carrying out sub-design division according to the module level of each module in a user netlist in combination with a first resource threshold sequence corresponding to an FPGA (Field Programmable Gate Array), and fitting the design logic clustering characteristics; according to the method, the hardware segmentation requirements of cross-sub-design interconnection and adaptation to multi-FPGA prototype verification are reduced, the layout and wiring difficulty is reduced, the performance and frequency of the FPGA are effectively improved, storage type allocation is realized according to the first target conversion rate and the second target conversion rate of the object and the target memory type, and the storage efficiency is improved. Relative balance and independence of various kinds of memory resources are achieved in the sub-design as much as possible, the number of FPGA chips needed for achieving the sub-design is reduced, and equivalently, the performance of the FPGA is improved.

The invention relates to the field of hardware simulation, and provides an encoding and decoding method, an encoder, a decoder, a programmable logic device and a hardware simulation system.The method is applied to a first PLD in the hardware simulation system, the hardware simulation system comprises a plurality of PLDs, and the method comprises the steps that an original data sequence is obtained, and the original data sequence comprises 6N pieces of original data; 6 pieces of original data in the 6N pieces of original data are coded through the coding matrix to obtain 4 pieces of coded data, the 6 pieces of original data are the 6i-5th to 6i-th pieces of original data in the original data sequence, and i is a positive integer smaller than or equal to N; a first data sequence is sent to a second PLD, the first data sequence comprises 10N pieces of first data, and the 10i-ninth to 10i pieces of first data in the first data sequence comprise 6 pieces of original data and 4 pieces of coded data. According to the method, error correction coding and decoding with low error rate and low time delay can be realized in a hardware simulation system.

The embodiments of the present application provide a chip simulation test method, device, equipment and system. The chip simulation test method includes: using a hardware simulation system to simulate the first part of the chip running the design program, and performing at least one sampling to obtain at least one sampling data; loading the at least one sampling data into the software simulation system; the software simulation system simulates the chip to continue to run part of the remaining program or all of the remaining program of the design program based on the at least one sampling data, so as to simulate the chip running the design program. The embodiment of the present application executes part of the program in the hardware simulation system, and the software simulation system continues to execute the design program based on the collected data, so that there is no need to actually execute the entire process of the design program. The hardware simulation system and the software simulation system can be combined to achieve efficient analysis and debugging, thereby providing good guidance for chip design.

The present application discloses a hardware simulation system, a control method, an electronic device, and a storage medium, relating to the technical field of simulation. Since the external process interface module, the synchronization core module, and the hardware simulation process interface module cooperate with each other, the external process interface module writes simulation data into the external push queue of the synchronization core module. When the conditions are met, the synchronization core module transfers the data to the local pull queue of the hardware simulation process interface module. The hardware simulation process can obtain the data by accessing the local pull queue. The entire process reduces the access conflict of shared resources. Therefore, the technical problem of the long locking time of shared resources between the hardware simulation process and the processes of other processor cores in the related art is solved, and the technical effect of improving the hardware simulation efficiency of integrated circuits is achieved.

An embodiment of the present invention provides a verification method, device, electronic device, and storage medium. Based on the module timing requirements corresponding to each module in the code file to be verified, the code file to be verified is divided into a first code file and a second code file; the module timing requirement of the first module included in the first code file is lower than the module timing requirement of the second module included in the second code file; the first code file is compiled into an executable file, and based on the executable file, software simulation verification is performed in a software simulation environment; the target bit file corresponding to the second code file is deployed to a specified chip, and based on the specified chip, hardware simulation verification is performed in a hardware simulation environment; the software simulation environment and the hardware simulation environment perform bidirectional data synchronization based on a target communication interface. By adopting a combined software and hardware verification method, while improving the verification effect, the verification advantages of the two verification methods are taken into account, and it has the advantages of convenient debugging and high verification accuracy.

The embodiment of the invention discloses a PCIe interrupt verification method and device, hardware simulation equipment and a medium, and relates to the field of chip verification. The method is executed by a hardware simulation device, the hardware simulation device runs a to-be-tested design and an interrupt processing engine, the to-be-tested design is an RTL code of a PCIe controller, and the method comprises the following steps: generating an interrupt signal triggered by a PCIe interrupt trigger event through the to-be-tested design; determining an interrupt processing mode of the interrupt signal through an interrupt processing engine; and performing interrupt processing on the interrupt signal according to the interrupt processing mode through an interrupt processing engine to obtain an interrupt processing result which is used for determining a verification result of the to-be-tested design. By adopting the PCIe interrupt verification method provided by the invention, the resource bottleneck caused by a host and a Speed Bridge in related technologies is eliminated, the verification efficiency and the test throughput are improved, and the feasibility of large-scale pressure test is realized.

The invention discloses a namespace management operation testing method and device, electronic equipment and a storage medium, and relates to the technical field of storage. The method comprises the steps of obtaining the number of processors of a target host corresponding to a target hardware simulation platform, the number of controllers of a target redundant array of independent disks, the number of redundant array of independent disks and the total capacity of each redundant array of independent disks; creating a plurality of threads consistent with the processors in number; determining configuration information corresponding to each thread according to the number of the controllers, the plurality of threads, the number of redundant array groups of independent disks and the total capacity; and based on the configuration information corresponding to each thread, calling the plurality of threads to send a management operation instruction to the target redundant array of independent disks in parallel, so that the target redundant array of independent disks executes a management operation test in parallel according to the received management operation instruction. The problem of low testing efficiency of management operation testing of the namespace is solved.

The application discloses a chip silicon pre-verification method and device, a hardware simulator and a medium, and belongs to the technical field of artificial intelligence chips. The method comprises the following steps: acquiring memory data from a physical accelerator; executing initial logic of a plurality of operators to be verified in a fixed order; testing the plurality of operators in sequence to obtain standard output results corresponding to the plurality of operators respectively; and storing the standard output results of each operator in the plurality of operators in target memories corresponding to the operators. When each verification operator is verified individually, the standard output results of the previous operator are directly acquired from the target memory corresponding to the previous operator as simulation input data of the verification operator, the reconstruction logic of the verification operator is executed, the first simulation output result of the verification operator is obtained, and the first verification result of the verification operator is determined. Each operator in an end-to-end system is disassembled, coupling between the operators is avoided, each operator does not need to be analyzed, the operator that fails to verify is accurately positioned, and the verification efficiency is improved.

The present invention belongs to the field of integrated circuit verification technology, and particularly relates to a PCIe bridge chip verification method based on a hardware simulation accelerator. It includes a PCIe bridge chip controller to be verified, a mode configuration module, a speed reduction bridge module suitable for a hardware simulation accelerator, and a commercial PCIe device, wherein one end of the speed reduction bridge module is connected to the commercial PCIe device through a gold finger, and the other end of the speed reduction bridge module is connected to the PCIe bridge chip controller to be verified through a standard PIPE interface. The mode configuration module is used to configure the number of group lanes, lane rate, PCIe controller working mode, and PIPE interface bit width and rate of the top wrapper of the speed reduction bridge module of the PCIe bridge chip controller to be verified. The present invention can realize multi-mode and full bandwidth performance verification of the PCIe bridge chip controller to be verified, shorten the engineering iteration cycle, and improve verification efficiency.

The present invention discloses a method for verifying a large message exceeding the memory capacity in a SOC sha unit, and belongs to the field of validity verification of functional units of a system chip. The method comprises: dividing a large message exceeding the memory capacity of the SOC into blocks; adding a first statement for sequentially loading each block in the SOC hardware simulation environment; adding a second statement for declaration and sha unit calculation in succession in the SOC embedded program; and using the first statement and the second statement to collaboratively verify the large message in the SOC sha unit. This scheme divides the large message into blocks, and the software program and the hardware simulation environment collaboratively complete the loading of multiple block messages and the SHA calculation in succession. Since the message content is directly loaded multiple times using hardware, there is no need to declare the large message in the embedded program, and no manual declaration is required, so that the automatic verification of the large message in the SOC sha unit whose message length is greater than the memory capacity of the SOC can be realized.

The invention provides a memory simulation method and device, equipment, a storage medium and a program product. The memory simulation method comprises the following steps: compiling a memory model and a plurality of simulation interfaces of the memory model in the hardware simulation platform; the method comprises the steps of determining a plurality of simulation interface combinations, establishing mapping between the simulation interface combinations and simulation storage positions, and determining a plurality of programming positions of first data according to the first data to be programmed; determining a first sequence based on the programming position and the simulation interface combination mapped by the programming position; second data are written into the first positions in the multiple first positions one by one, and the set data written into the multiple first positions form first data programmed in the memory model. According to the method and the device, the process of writing data into the first position mapped by the simulation interface combination one by one can be displayed.

According to the SR-IOV testing method and system based on the hardware simulation acceleration platform and the extended virtual machine, an additional hardware device is carried on the hardware simulation acceleration platform, the device can achieve extension of hardware resources, and the hardware simulation acceleration platform is driven and communicated through customized software, so that the hardware simulation acceleration platform and the extended virtual machine are integrated. According to the technical scheme, operation of a plurality of virtual machines and single-port or dual-port data communication are supported, full testing of the SR-IOV function is achieved, and the testing efficiency and the convenience degree of SR-IOV testing are improved.

The present invention belongs to the technical field of FPGA integrated electronic design automation, and specifically relates to an FPGA technology mapping algorithm based on logic gate decomposition. In the process of technology mapping, the algorithm of the present invention selectively performs logic gate decomposition to optimize the area and timing performance of the synthesized circuit; the algorithm simultaneously executes wide logic gate decomposition and K-cut enumeration mapping; when performing mapping, it dynamically generates the decomposition form of wide logic gates according to the mapping requirements, avoiding the contradiction between the number of decompositions and the optimization effect caused by pre-logic gate decomposition, and achieving the purpose of shortening the calculation time and obtaining better optimization effects at the same time. The present invention is applicable to both the development of FPGA integrated EDA tools and the development of EDA tools for FPGA hardware simulation systems. The idea of logic gate decomposition and technology mapping of the present invention is also applicable to the development of ASIC technology mapping algorithms and EDA tools.

The utility model relates to the technical field of automobile automatic driving simulation test, and specifically discloses a hardware-in-the-loop simulation test platform for automatic driving development. The platform comprises a simulation environment, a simulation module and automatic driving vehicle hardware, the simulation module is one or more vehicle dynamics simulation modules and is embedded in the simulation environment; the automatic driving vehicle hardware is single automatic driving function hardware or a hardware system composed of a plurality of automatic driving function hardware; the automatic driving vehicle hardware is connected with the simulation environment and the simulation module, the simulation environment outputs a simulated environment signal as sensing data input of the simulation module, and a processing result of the simulation module is transmitted to the automatic driving vehicle hardware, so that the automatic driving vehicle hardware generates a corresponding hardware signal and feeds the hardware signal into the simulation environment. According to the utility model, hardware of a real automatic driving vehicle, a simulation environment and a simulation module are integrated into a complete hardware-in-the-loop simulation test platform, and an automatic driving function can be effectively verified.