65 results about "Hardware emulation" patented technology

A hardware emulator and an emulation system including the hardware emulator are provided. The hardware emulator includes an artificial neural network-based reconstruction model configured to reconstruct dynamics of a dynamical system based on input data and a memristor-based circuit configured to emulate state space representation of the dynamical system based on the reconstruction model.

The invention provides an artificial intelligence chip pre-silicon verification system and method, and relates to the technical field of artificial intelligence chips, and the system comprises a model importing layer which is used for importing a current model; the model analysis layer is used for analyzing the current model to obtain a calculation graph; the distributed strategy configuration layer is used for configuring a distributed topology strategy of a hardware simulator of the artificial intelligence chip based on the distributed strategy of the current model, and adjusting a computational graph of the current model to enable the computational graph to be matched with the distributed topology strategy; the performance prediction layer is used for determining the operation performance data of the current model in the artificial intelligence chip based on the operation performance data of each operator; or determining a performance prediction result of the current model in the artificial intelligence chip based on the performance prediction result of each operator; and the operator implementation layer is used for controlling the hardware simulator to run each operator in the computational graph. According to the system and the method provided by the invention, the end-to-end whole-process verification from model input to result output is carried out on the artificial intelligence chip.

The invention provides a universal serial bus (USB) 2.0 host speed reduction bridge based on bidirectional protocol handshake and a prototype verification or hardware simulation acceleration platform, which are characterized in that a slow-speed side module runs at a slow clock frequency, is responsible for realizing a protocol layer of a USB protocol and a physical link layer function of the USB protocol, and communicates with a USB2.0 host controller in a chip design (DUT) to be tested; the original speed side module works under the original clock frequency, logic of a protocol layer of a USB protocol and a physical link layer of the USB protocol is achieved, communication with an external real USB2.0 slave end device is achieved through a USB2.0 PHY, data caching and synchronization are achieved through a data caching RAM, and the bridge control module overall plans the whole situation and accurately regulates and controls independent handshake of the USB2.0 protocol layers on the two sides under the original clock frequency. Through bidirectional protocol handshake on the two sides of the speed reduction bridge, data communication between a low-speed to-be-tested chip design (DUT) in a chip prototype verification platform and external standard-speed real USB slave equipment is achieved through the speed reduction bridge.

The invention relates to a hardware simulation accelerator multi-user access method, system and device and a storage medium, and is applied to the technical field of hardware simulation accelerators, and the method comprises the following steps: distributing a plurality of resource blocks for different users in a hardware simulation accelerator to obtain a user resource block corresponding table; virtualizing the plurality of PCIe devices in the host interface card to obtain a plurality of mutually independent virtual function devices; constructing a plurality of device driving programs corresponding to the plurality of virtual function devices in the host server; binding a plurality of corresponding equipment driving programs for different users in the host server to obtain equipment driving program binding information; and performing multi-user access of the hardware simulation accelerator according to the user resource block corresponding table, the device driver binding information and the plurality of virtual function devices. The method has the technical effect that the multi-user access to the hardware simulation accelerator can be realized faster and more stably.

The invention discloses a software and hardware co-simulation field recovery method and device, equipment and a medium. Comprising the steps of defining a recording starting point and a storage time point of a simulation site; from the recording starting point to the storage time point, capturing transaction flow and causal metadata from the hardware simulation environment of the simulation site to the software test platform, and meanwhile, storing a state snapshot of the verified design in the hardware simulation environment; and when a recovery instruction is received, performing simulation field recovery based on the transaction flow, the causal metadata and the state snapshot. By defining the time range of data capture, a clear boundary is delimited for subsequent data storage, and pertinence and integrity of data records are ensured. A basis is provided for semantic reconstruction of a software test platform by capturing a transaction flow and causal metadata, a state snapshot ensures that the verified design hardware state can be accurately restored, and complete storage of recovery data on the two sides of software and hardware is achieved. And the system does not need to be restarted from the starting point during recovery, so that a redundancy initialization process is avoided, and the simulation debugging efficiency is improved.

The invention provides a low-power-consumption simulation method and device, equipment, a storage medium and a program product, and relates to the technical field of integrated circuits. The method comprises the following steps: determining an initial comprehensive model of a register transfer level corresponding to a to-be-simulated chip; based on the initial comprehensive model, determining a target comprehensive model corresponding to the to-be-simulated chip; according to the initial gate-level netlist corresponding to the to-be-simulated chip, generating a target gate-level netlist corresponding to a power supply loop in low-power-consumption simulation; and based on a preset hardware simulation accelerator, performing low-power-consumption simulation including a power supply loop on the target synthesizable model and the target gate-level netlist. According to the method, the low-power-consumption simulation convergence time is greatly shortened, and the simulation efficiency is improved.

A method includes receiving, by a processing device, receiving a data file, dividing the data file into a plurality of partitions based on a defined criteria, compiling the plurality of partitions associated with the data file to form a plurality of compiled partitions, generating a status identifier for each of the plurality of partitions, wherein the status identifier reflects a current version of a corresponding partition. The method further includes combining the plurality of compiled partitions to form a first executable file, and storing the plurality of compiled partitions and a corresponding status identifier for each of the plurality of compiled partitions in a first storage area of a first storage medium. The method also includes receiving a request for the data file, identifying that one or more partitions of the plurality of partitions is reusable, and sending the one or more partitions identified as being reusable.

The invention relates to an embedded chip simulation and debugging method and system. The method comprises the following steps: expanding an instruction decoding module, a register description module and a breakpoint management module which support a C28x instruction set in a GDB debugger, and generating a special debugging front-end program; the method comprises the following steps: expanding a C28x JTAG protocol adaptation module in an OpenOCD debugging agent, and generating a debugging agent program; a C28x instruction set execution simulation unit is realized in the NEMU simulator, and a GDB Server communication module is embedded in the NEMU simulator; seamless switching between a simulation debugging mode and a hardware debugging mode is realized based on a unified configuration file through a software and hardware debugging environment rapid switching control module. The problems that a traditional debugging mode depends on a special hardware simulator, the cost is high and the simulation environment is inaccurate are solved, and through an integrated software and hardware collaborative debugging scheme, the debugging cost is greatly reduced, and the development efficiency and the comprehensiveness of system verification are improved.

The invention provides an automatic driving formation hardware-in-the-loop simulation platform based on a satellite position simulation platform and a medium, and relates to the technical field of automatic driving and car networking simulation. The platform comprises a satellite position simulation module, a traffic simulation platform, a hardware verification platform, a simulation bus and a clock synchronization module. The satellite position simulation module generates satellite data with a timestamp; the traffic simulation platform constructs a formation driving scene and operates a formation control algorithm; the hardware verification platform comprises a real phased-array antenna module and a PC5 communication device. The modules exchange data through a simulation bus, and the clock synchronization module unifies the time reference to form a closed-loop verification environment of simulation hardware simulation. The problems that space-based data and ground simulation are separated and real communication characteristics are difficult to quantitatively evaluate in the prior art are solved, the satellite-ground cooperation and formation control strategy can be efficiently and reliably verified in a laboratory environment, and the real vehicle test cost and risk are remarkably reduced.

The invention relates to the technical field of chip design simulation verification, in particular to a memory type dynamic determination method for prototype verification and hardware simulation, and the method comprises the steps: carrying out sub-design division according to the module level of each module in a user netlist in combination with a first resource threshold sequence corresponding to an FPGA (Field Programmable Gate Array), and fitting the design logic clustering characteristics; according to the method, the hardware segmentation requirements of cross-sub-design interconnection and adaptation to multi-FPGA prototype verification are reduced, the layout and wiring difficulty is reduced, the performance and frequency of the FPGA are effectively improved, storage type allocation is realized according to the first target conversion rate and the second target conversion rate of the object and the target memory type, and the storage efficiency is improved. Relative balance and independence of various kinds of memory resources are achieved in the sub-design as much as possible, the number of FPGA chips needed for achieving the sub-design is reduced, and equivalently, the performance of the FPGA is improved.

The embodiment of the invention discloses a PCIe interrupt verification method and device, hardware simulation equipment and a medium, and relates to the field of chip verification. The method is executed by a hardware simulation device, the hardware simulation device runs a to-be-tested design and an interrupt processing engine, the to-be-tested design is an RTL code of a PCIe controller, and the method comprises the following steps: generating an interrupt signal triggered by a PCIe interrupt trigger event through the to-be-tested design; determining an interrupt processing mode of the interrupt signal through an interrupt processing engine; and performing interrupt processing on the interrupt signal according to the interrupt processing mode through an interrupt processing engine to obtain an interrupt processing result which is used for determining a verification result of the to-be-tested design. By adopting the PCIe interrupt verification method provided by the invention, the resource bottleneck caused by a host and a Speed Bridge in related technologies is eliminated, the verification efficiency and the test throughput are improved, and the feasibility of large-scale pressure test is realized.

The invention discloses a namespace management operation testing method and device, electronic equipment and a storage medium, and relates to the technical field of storage. The method comprises the steps of obtaining the number of processors of a target host corresponding to a target hardware simulation platform, the number of controllers of a target redundant array of independent disks, the number of redundant array of independent disks and the total capacity of each redundant array of independent disks; creating a plurality of threads consistent with the processors in number; determining configuration information corresponding to each thread according to the number of the controllers, the plurality of threads, the number of redundant array groups of independent disks and the total capacity; and based on the configuration information corresponding to each thread, calling the plurality of threads to send a management operation instruction to the target redundant array of independent disks in parallel, so that the target redundant array of independent disks executes a management operation test in parallel according to the received management operation instruction. The problem of low testing efficiency of management operation testing of the namespace is solved.

The application discloses a chip silicon pre-verification method and device, a hardware simulator and a medium, and belongs to the technical field of artificial intelligence chips. The method comprises the following steps: acquiring memory data from a physical accelerator; executing initial logic of a plurality of operators to be verified in a fixed order; testing the plurality of operators in sequence to obtain standard output results corresponding to the plurality of operators respectively; and storing the standard output results of each operator in the plurality of operators in target memories corresponding to the operators. When each verification operator is verified individually, the standard output results of the previous operator are directly acquired from the target memory corresponding to the previous operator as simulation input data of the verification operator, the reconstruction logic of the verification operator is executed, the first simulation output result of the verification operator is obtained, and the first verification result of the verification operator is determined. Each operator in an end-to-end system is disassembled, coupling between the operators is avoided, each operator does not need to be analyzed, the operator that fails to verify is accurately positioned, and the verification efficiency is improved.

The invention provides a memory simulation method and device, equipment, a storage medium and a program product. The memory simulation method comprises the following steps: compiling a memory model and a plurality of simulation interfaces of the memory model in the hardware simulation platform; the method comprises the steps of determining a plurality of simulation interface combinations, establishing mapping between the simulation interface combinations and simulation storage positions, and determining a plurality of programming positions of first data according to the first data to be programmed; determining a first sequence based on the programming position and the simulation interface combination mapped by the programming position; second data are written into the first positions in the multiple first positions one by one, and the set data written into the multiple first positions form first data programmed in the memory model. According to the method and the device, the process of writing data into the first position mapped by the simulation interface combination one by one can be displayed.

The invention provides a method for simulating logic system design on a hardware simulation tool, and the method comprises the steps: receiving a simulation mode instruction which comprises a first instruction used for enabling the hardware simulation tool to be in a prototype verification mode or a second instruction used for enabling the hardware simulation tool to be in a debugging mode; in response to the received first instruction, enabling the hardware simulation tool to run in the prototype verification mode; and responding to the received second instruction, and enabling the hardware simulation tool to run in the debugging mode.

The invention relates to the technical field of computers, in particular to a software and hardware simulation scheduling method and device, electronic equipment and a storage medium. According to the application, the scheduling demand is directly sent through the software control end, the hardware simulation end analyzes and processes through the scheduling controller and generates the instruction, the instruction is converted into the scheduling logic of the hardware simulation assembly through the operation control module, and finally the hardware simulation assembly completes function simulation. According to the architecture, clear division and efficient intercommunication of software and hardware environments are realized, and low interaction efficiency and insufficient flexibility caused by environment isolation of a virtual platform are avoided; and through specialized function simulation of the hardware simulation assembly, sufficiency of hardware simulation is ensured, meanwhile, code roles of all modules are clearly defined, and the problem that a function calling platform is difficult to expand and maintain is solved. Therefore, according to the scheme, the requirements of chip software and hardware interaction verification for high efficiency and accuracy can be met, and the test preparation efficiency and verification reliability are improved.

The present application relates to a memory sequence verification and acceleration method, system, computer device and storage medium, the method of the present application is simplified to RISC-V processor core and system on chip, the scale of hardware simulation is reduced, and the simulation time of the verification case is shortened in the mode of converting the signal request sequence on the memory interface, at the same time, according to the FPGA platform, the top layer of the verification platform is compiled and tested, the effect of FPGA hardware acceleration can be maximized, so that the verification efficiency is improved.

The invention discloses a verification system based on simulation interaction of an SOC software system and UVM hardware, and the system comprises an SOC side multi-core CPU module which is used for transmitting a control command in a predefined format to a UVM environment through a standard AMBA bus interface; the command parsing Agent module in the UVM environment is used for capturing and parsing the control command and realizing multi-core concurrency control of the SOC side multi-core CPU module through a thread ID routing mechanism, an independent command queue buffer and an atomic operation lock; and the verification component is used for executing the analyzed control command and writing a result into a predefined feedback address. According to the method, accurate distribution of the multi-core commands is realized through a thread ID routing mechanism, the stability of concurrency control is guaranteed by combining independent command queue buffering and an atomic operation lock, the problems of insufficient standardization of communication interfaces, conflict of the multi-core commands and high delay of information interaction in the prior art are effectively solved, and the method is suitable for popularization and application. The method has the advantages that the verification efficiency is improved, the multi-core concurrency control reliability is ensured, and the software and hardware interaction process is simplified.

Embodiments of the present application provide a kind of MVB automation experiment configuration system and method, electronic equipment, storage medium, the system includes: multiple vehicle real unit, the vehicle real unit has MVB communication port;Emulator is equipped with multiple MVB simulation communication interface;Program-controlled multiplex switch matrix, electrically connected the MVB communication port of vehicle real unit with the emulator, for controlling the on-off of communication link between each port;First control unit, for receiving the topology demand instruction of host computer, and according to the instruction control the state switching of corresponding switch in the program-controlled multiplex switch matrix, to realize the automation physical connection configuration of MVB network, can be realized by program-controlled switch matrix the automation configuration connection of MVB bus, so that the measured train network system can be according to simulation test demand, automation, quickly, flexibly configure hardware simulation resource, to improve test efficiency and reliability.

The present application relates to chip design technical field, especially to a kind of debugging system based on hardware simulation, it includes M target module, each target module includes K processing unit and a capture module, each processing unit includes at least one node;Capture module includes mask module, K filter, packing module and cache module;Wherein mask module is used to obtain the target node specified by user;Each filter is connected mask module respectively, and each filter connects a processing unit;For screening out the target data of target node in the data stream of corresponding processor, packing module connects all filters, for packing target data;Data cache module connects packing module, for caching the target data after packing and sending to memory. Wherein the number of target node specified by user is not limited by hardware, when user specifies more than preset number of processing unit or changes target node, it is not necessary to recompile, improve debugging efficiency.

The embodiment of the invention provides a simulation test method, a simulation test device, a simulation test system, electronic equipment, a computer storage medium and a computer program product. The simulation test method comprises the steps that a preset random constraint component is called, random excitation parameters meeting input constraint conditions are generated, and the preset random constraint component is used for executing randomization processing according to the input constraint conditions; importing the random excitation parameter into a test development environment, and calling the random excitation parameter to generate a test case; loading the test case to a hardware simulation environment of a chip to be tested; and performing a simulation test on the to-be-tested chip in the hardware simulation environment by using the test case.

The invention discloses a hardware simulation-based performance test system, a hardware simulator and a test method, and relates to the technical field of chip design. The system comprises a request generation module, a protocol core module, a data stream sending module and a to-be-tested equipment simulation module, the request generation module is used for generating a test request of the data bus system according to the loaded executable file, and the test request is used for testing the data bus system; the protocol core module is used for converting the test request into a test message and converting the test message into a transmission data stream, and the test message conforms to a bus protocol corresponding to the data bus system; and the data stream sending module is used for sending the transmission data stream to the to-be-tested equipment simulation module, and the to-be-tested equipment simulation module is used for simulating equipment using the data bus system. Real physical equipment is simulated through the performance test system based on hardware simulation so as to test the data bus system, and the test accuracy of the data bus system can be improved.

The invention provides a performance analysis method and device, electronic equipment and a computer readable storage medium, and the method comprises the steps: obtaining a test instruction sequence, and converting the test instruction sequence into a physical signal and a program calling signal; the test instruction sequence comprises a plurality of test instructions, and the test instructions are used for testing the function of the to-be-tested design; the physical signal is matched with a hardware simulation model to be tested and designed; the program calling signal is matched with a to-be-tested designed software simulation model; driving a hardware simulation model of the to-be-tested design to operate according to the physical signal to obtain first operation performance data of the to-be-tested design; driving a software simulation model of the to-be-tested design to run according to the program calling signal to obtain second running performance data of the to-be-tested design; and determining a performance analysis result of the to-be-tested design according to the first operation performance data and the second operation performance data. According to the embodiment of the invention, the total project period can be shortened, the performance analysis efficiency is improved, and the performance analysis complexity is reduced.

The invention discloses a simulation debugging system and method and a computer readable storage medium, the simulation debugging system comprises a host and a hardware simulation acceleration platform, the host comprises a first high-speed serial interface subsystem, and the hardware simulation acceleration platform comprises a programmable logic device; the programmable logic device is used for receiving debugging information forwarded by a debugging and testing subsystem in the tested equipment; performing format conversion on each piece of debugging information to obtain each piece of debugging information after format conversion; coding each piece of debugging information after format conversion to obtain each piece of coded debugging information; each piece of coded debugging information is returned to the debugging and testing subsystem; the host is used for receiving each piece of coded debugging information sent by the debugging and testing subsystem through the second high-speed serial interface subsystem through the first high-speed serial interface subsystem; and decoding each piece of coded debugging information, and carrying out simulation debugging according to the obtained decoded debugging information. According to the method, the simulation debugging time is shortened, debugging information transmission of multiple devices is supported, and computing resources are saved.

The invention provides a virtuality and reality combined fault mode simulation verification system and method. The system comprises a fault analysis module which is used for identifying a fault mode, analyzing cause influence, formulating an avoidance mechanism and summarizing a fault type, harm and probability in combination with system requirements, a function principle and an operation environment; the fault mode library management module is used for establishing a library according to an analysis result, graphically displaying fault performance and establishing child nodes of reasons, influences, monitoring mechanisms and improvement measures; the fault scene virtual-real simulation module is used for building a typical scene library according to fault reasons and realizing hard / full digital simulation; and the fault diagnosis test module is used for adjusting the model and to-be-diagnosed data to verify redundancy recovery capability, managing tasks, providing a visual chart and automatically associating fault modes. According to the method, fault mechanism analysis and closed-loop verification from library establishment to software and hardware simulation are realized, redundancy design of the spaceflight control system is supported, design and fault processing effects are verified, and high reliability and stability of the system are guaranteed.

The invention relates to the field of SSD main control chip research and development, in particular to an SSD performance test system and method. The test system comprises a data compression storage module, a parallel computing module, a computing resource optimization distribution module and a data analysis and calibration module which are deployed on a hardware simulation acceleration platform. The parallel computing module monitors read-write performance data in the virtual host in real time and distinguishes non-key waveforms and key waveforms, and the data compression storage module discards the non-key waveforms and compresses, classifies and stores the key waveforms; the data analysis and calibration module firstly analyzes the stored key waveform to obtain performance data; then the analysis result is corrected according to the calibration model; and the computing resource optimization distribution module dynamically distributes computing resources of the FPGA platform according to the priority and the computing complexity of the waveform analysis task. According to the invention, the SSD performance test efficiency and accuracy can be improved.

Embodiments of the present application provide a chip simulation verification system and method, the chip simulation verification system comprising: a front-end server, a hardware simulation accelerator and at least one interface extender; the front-end server is provided with at least one first interface, the first interface is configured to be connected with a second interface on an interface extender, each interface extender comprises a second interface and at least two third interfaces connected with the second interface; the hardware simulation accelerator comprises at least two simulation units, each simulation unit is connected with a third interface, and different simulation units are connected with different third interfaces; the simulation unit is used for simulating a chip to be verified; the front-end server is used for communicating with each simulation unit through the interface extender respectively, and verifying the chip to be verified simulated by each simulation unit. The present scheme can improve the applicability of chip simulation verification.

The invention provides a software and hardware combined simulation system and method, the simulation system comprises a software simulation domain and a hardware simulation domain, the software simulation domain comprises a plurality of processor cores and a software bridge, and the hardware simulation domain comprises a hardware bridge and peripheral equipment. The software simulation domain of the system is responsible for transaction scheduling and global time advancing, the advantage of high simulation speed of software simulation is fully utilized, meanwhile, hardware simulation is carried out on peripheral equipment through the hardware simulation domain of the system, real delay feedback and bandwidth characteristics can be provided, and the hardware simulation speed of the peripheral equipment is improved. The advantage of high simulation precision of hardware simulation is fully utilized, so that collaborative design of simulation precision and simulation speed is realized through combination of software and hardware.

The present application relates to the technical field of electronic design automation, in particular to a method for obtaining an intermediate state simulation framework, a storage medium and an electronic device, which extracts a hardware simulator generated software and hardware interaction running framework, a first host end component and a simulator end hardware design module; respectively obtains a preset simulator end clock controlled behavior level reference model, a preset simulator end hardware interaction interface behavior level reference model specially used for interaction with the first host end; constructs a multiplexing running framework intermediate state simulation framework, including a second host end multiplexing the first host end component and a simulation end multiplexing the hardware design module, the hardware design module communicates with the second host end through the behavior level reference model of the hardware interaction interface, the clock behavior of the hardware design module and the behavior level reference model of the hardware interaction interface is modeled by the clock controlled behavior level reference model, achieving the purpose of improving the debugging capability and reducing the compilation iteration time.