38 results about "Hardware emulation" patented technology

The invention relates to a hardware simulation accelerator multi-user access method, system and device and a storage medium, and is applied to the technical field of hardware simulation accelerators, and the method comprises the following steps: distributing a plurality of resource blocks for different users in a hardware simulation accelerator to obtain a user resource block corresponding table; virtualizing the plurality of PCIe devices in the host interface card to obtain a plurality of mutually independent virtual function devices; constructing a plurality of device driving programs corresponding to the plurality of virtual function devices in the host server; binding a plurality of corresponding equipment driving programs for different users in the host server to obtain equipment driving program binding information; and performing multi-user access of the hardware simulation accelerator according to the user resource block corresponding table, the device driver binding information and the plurality of virtual function devices. The method has the technical effect that the multi-user access to the hardware simulation accelerator can be realized faster and more stably.

The invention discloses a software and hardware co-simulation field recovery method and device, equipment and a medium. Comprising the steps of defining a recording starting point and a storage time point of a simulation site; from the recording starting point to the storage time point, capturing transaction flow and causal metadata from the hardware simulation environment of the simulation site to the software test platform, and meanwhile, storing a state snapshot of the verified design in the hardware simulation environment; and when a recovery instruction is received, performing simulation field recovery based on the transaction flow, the causal metadata and the state snapshot. By defining the time range of data capture, a clear boundary is delimited for subsequent data storage, and pertinence and integrity of data records are ensured. A basis is provided for semantic reconstruction of a software test platform by capturing a transaction flow and causal metadata, a state snapshot ensures that the verified design hardware state can be accurately restored, and complete storage of recovery data on the two sides of software and hardware is achieved. And the system does not need to be restarted from the starting point during recovery, so that a redundancy initialization process is avoided, and the simulation debugging efficiency is improved.

A method includes receiving, by a processing device, receiving a data file, dividing the data file into a plurality of partitions based on a defined criteria, compiling the plurality of partitions associated with the data file to form a plurality of compiled partitions, generating a status identifier for each of the plurality of partitions, wherein the status identifier reflects a current version of a corresponding partition. The method further includes combining the plurality of compiled partitions to form a first executable file, and storing the plurality of compiled partitions and a corresponding status identifier for each of the plurality of compiled partitions in a first storage area of a first storage medium. The method also includes receiving a request for the data file, identifying that one or more partitions of the plurality of partitions is reusable, and sending the one or more partitions identified as being reusable.

The invention relates to an embedded chip simulation and debugging method and system. The method comprises the following steps: expanding an instruction decoding module, a register description module and a breakpoint management module which support a C28x instruction set in a GDB debugger, and generating a special debugging front-end program; the method comprises the following steps: expanding a C28x JTAG protocol adaptation module in an OpenOCD debugging agent, and generating a debugging agent program; a C28x instruction set execution simulation unit is realized in the NEMU simulator, and a GDB Server communication module is embedded in the NEMU simulator; seamless switching between a simulation debugging mode and a hardware debugging mode is realized based on a unified configuration file through a software and hardware debugging environment rapid switching control module. The problems that a traditional debugging mode depends on a special hardware simulator, the cost is high and the simulation environment is inaccurate are solved, and through an integrated software and hardware collaborative debugging scheme, the debugging cost is greatly reduced, and the development efficiency and the comprehensiveness of system verification are improved.

The invention provides an automatic driving formation hardware-in-the-loop simulation platform based on a satellite position simulation platform and a medium, and relates to the technical field of automatic driving and car networking simulation. The platform comprises a satellite position simulation module, a traffic simulation platform, a hardware verification platform, a simulation bus and a clock synchronization module. The satellite position simulation module generates satellite data with a timestamp; the traffic simulation platform constructs a formation driving scene and operates a formation control algorithm; the hardware verification platform comprises a real phased-array antenna module and a PC5 communication device. The modules exchange data through a simulation bus, and the clock synchronization module unifies the time reference to form a closed-loop verification environment of simulation hardware simulation. The problems that space-based data and ground simulation are separated and real communication characteristics are difficult to quantitatively evaluate in the prior art are solved, the satellite-ground cooperation and formation control strategy can be efficiently and reliably verified in a laboratory environment, and the real vehicle test cost and risk are remarkably reduced.

The invention relates to the technical field of chip design simulation verification, in particular to a memory type dynamic determination method for prototype verification and hardware simulation, and the method comprises the steps: carrying out sub-design division according to the module level of each module in a user netlist in combination with a first resource threshold sequence corresponding to an FPGA (Field Programmable Gate Array), and fitting the design logic clustering characteristics; according to the method, the hardware segmentation requirements of cross-sub-design interconnection and adaptation to multi-FPGA prototype verification are reduced, the layout and wiring difficulty is reduced, the performance and frequency of the FPGA are effectively improved, storage type allocation is realized according to the first target conversion rate and the second target conversion rate of the object and the target memory type, and the storage efficiency is improved. Relative balance and independence of various kinds of memory resources are achieved in the sub-design as much as possible, the number of FPGA chips needed for achieving the sub-design is reduced, and equivalently, the performance of the FPGA is improved.

The application discloses a chip silicon pre-verification method and device, a hardware simulator and a medium, and belongs to the technical field of artificial intelligence chips. The method comprises the following steps: acquiring memory data from a physical accelerator; executing initial logic of a plurality of operators to be verified in a fixed order; testing the plurality of operators in sequence to obtain standard output results corresponding to the plurality of operators respectively; and storing the standard output results of each operator in the plurality of operators in target memories corresponding to the operators. When each verification operator is verified individually, the standard output results of the previous operator are directly acquired from the target memory corresponding to the previous operator as simulation input data of the verification operator, the reconstruction logic of the verification operator is executed, the first simulation output result of the verification operator is obtained, and the first verification result of the verification operator is determined. Each operator in an end-to-end system is disassembled, coupling between the operators is avoided, each operator does not need to be analyzed, the operator that fails to verify is accurately positioned, and the verification efficiency is improved.

The invention provides a method for simulating logic system design on a hardware simulation tool, and the method comprises the steps: receiving a simulation mode instruction which comprises a first instruction used for enabling the hardware simulation tool to be in a prototype verification mode or a second instruction used for enabling the hardware simulation tool to be in a debugging mode; in response to the received first instruction, enabling the hardware simulation tool to run in the prototype verification mode; and responding to the received second instruction, and enabling the hardware simulation tool to run in the debugging mode.

The invention discloses a verification system based on simulation interaction of an SOC software system and UVM hardware, and the system comprises an SOC side multi-core CPU module which is used for transmitting a control command in a predefined format to a UVM environment through a standard AMBA bus interface; the command parsing Agent module in the UVM environment is used for capturing and parsing the control command and realizing multi-core concurrency control of the SOC side multi-core CPU module through a thread ID routing mechanism, an independent command queue buffer and an atomic operation lock; and the verification component is used for executing the analyzed control command and writing a result into a predefined feedback address. According to the method, accurate distribution of the multi-core commands is realized through a thread ID routing mechanism, the stability of concurrency control is guaranteed by combining independent command queue buffering and an atomic operation lock, the problems of insufficient standardization of communication interfaces, conflict of the multi-core commands and high delay of information interaction in the prior art are effectively solved, and the method is suitable for popularization and application. The method has the advantages that the verification efficiency is improved, the multi-core concurrency control reliability is ensured, and the software and hardware interaction process is simplified.

The present application relates to chip design technical field, especially to a kind of debugging system based on hardware simulation, it includes M target module, each target module includes K processing unit and a capture module, each processing unit includes at least one node;Capture module includes mask module, K filter, packing module and cache module;Wherein mask module is used to obtain the target node specified by user;Each filter is connected mask module respectively, and each filter connects a processing unit;For screening out the target data of target node in the data stream of corresponding processor, packing module connects all filters, for packing target data;Data cache module connects packing module, for caching the target data after packing and sending to memory. Wherein the number of target node specified by user is not limited by hardware, when user specifies more than preset number of processing unit or changes target node, it is not necessary to recompile, improve debugging efficiency.

The invention discloses a hardware simulation-based performance test system, a hardware simulator and a test method, and relates to the technical field of chip design. The system comprises a request generation module, a protocol core module, a data stream sending module and a to-be-tested equipment simulation module, the request generation module is used for generating a test request of the data bus system according to the loaded executable file, and the test request is used for testing the data bus system; the protocol core module is used for converting the test request into a test message and converting the test message into a transmission data stream, and the test message conforms to a bus protocol corresponding to the data bus system; and the data stream sending module is used for sending the transmission data stream to the to-be-tested equipment simulation module, and the to-be-tested equipment simulation module is used for simulating equipment using the data bus system. Real physical equipment is simulated through the performance test system based on hardware simulation so as to test the data bus system, and the test accuracy of the data bus system can be improved.

The invention relates to the field of SSD main control chip research and development, in particular to an SSD performance test system and method. The test system comprises a data compression storage module, a parallel computing module, a computing resource optimization distribution module and a data analysis and calibration module which are deployed on a hardware simulation acceleration platform. The parallel computing module monitors read-write performance data in the virtual host in real time and distinguishes non-key waveforms and key waveforms, and the data compression storage module discards the non-key waveforms and compresses, classifies and stores the key waveforms; the data analysis and calibration module firstly analyzes the stored key waveform to obtain performance data; then the analysis result is corrected according to the calibration model; and the computing resource optimization distribution module dynamically distributes computing resources of the FPGA platform according to the priority and the computing complexity of the waveform analysis task. According to the invention, the SSD performance test efficiency and accuracy can be improved.

Embodiments of the present application provide a chip simulation verification system and method, the chip simulation verification system comprising: a front-end server, a hardware simulation accelerator and at least one interface extender; the front-end server is provided with at least one first interface, the first interface is configured to be connected with a second interface on an interface extender, each interface extender comprises a second interface and at least two third interfaces connected with the second interface; the hardware simulation accelerator comprises at least two simulation units, each simulation unit is connected with a third interface, and different simulation units are connected with different third interfaces; the simulation unit is used for simulating a chip to be verified; the front-end server is used for communicating with each simulation unit through the interface extender respectively, and verifying the chip to be verified simulated by each simulation unit. The present scheme can improve the applicability of chip simulation verification.

The invention provides a software and hardware combined simulation system and method, the simulation system comprises a software simulation domain and a hardware simulation domain, the software simulation domain comprises a plurality of processor cores and a software bridge, and the hardware simulation domain comprises a hardware bridge and peripheral equipment. The software simulation domain of the system is responsible for transaction scheduling and global time advancing, the advantage of high simulation speed of software simulation is fully utilized, meanwhile, hardware simulation is carried out on peripheral equipment through the hardware simulation domain of the system, real delay feedback and bandwidth characteristics can be provided, and the hardware simulation speed of the peripheral equipment is improved. The advantage of high simulation precision of hardware simulation is fully utilized, so that collaborative design of simulation precision and simulation speed is realized through combination of software and hardware.

The present application relates to the technical field of electronic design automation, in particular to a method for obtaining an intermediate state simulation framework, a storage medium and an electronic device, which extracts a hardware simulator generated software and hardware interaction running framework, a first host end component and a simulator end hardware design module; respectively obtains a preset simulator end clock controlled behavior level reference model, a preset simulator end hardware interaction interface behavior level reference model specially used for interaction with the first host end; constructs a multiplexing running framework intermediate state simulation framework, including a second host end multiplexing the first host end component and a simulation end multiplexing the hardware design module, the hardware design module communicates with the second host end through the behavior level reference model of the hardware interaction interface, the clock behavior of the hardware design module and the behavior level reference model of the hardware interaction interface is modeled by the clock controlled behavior level reference model, achieving the purpose of improving the debugging capability and reducing the compilation iteration time.

The invention discloses a dynamic heat effect simulation method and device of a micro-ring modulator, and belongs to the technical field of optical communication device simulation. The method comprises the following steps: dynamically calculating time-domain temperature rise based on a relaxation equation by separating three heat sources, namely heater heat production of a micro-ring modulator, electric driving Joule heat and in-ring light absorption heat, and updating resonant wavelength in real time in combination with a thermo-optic effect; and a coupling mode theory and a heat effect model are linked to construct a voltage-heat-light multi-physics field coupling framework. Based on the method, a Verilog-A hardware behavior level model is realized, and time domain iteration and dynamic temperature drift adaptation are supported. According to the method, the problems of heat effect staticizing and difficulty in distinguishing multi-heat-source response differences in micro-ring modulator simulation are solved in the field of optical communication, meanwhile, conversion from a physical model to hardware simulation is realized, and the design reliability and engineering reusability of a micro-ring modulator system are improved.

The invention provides an intelligent cockpit voice interaction test platform based on hardware simulation. The intelligent cockpit voice interaction test platform comprises driving simulator hardware used for providing a driving control environment close to a real vehicle and a human-computer interaction interface; the voice interaction test box is used for collecting voice signals in a cockpit, the simulation software module is used for constructing a virtual driving scene containing roads, traffic events and noise environments, the data collecting and processing module is used for synchronously collecting and recording voice interaction process data from the voice interaction test box, and the evaluation and report generation module is used for generating a report. And the analysis and calculation module is used for automatically analyzing and calculating the collected data according to a preset quantitative evaluation index system to generate a test report. According to the invention, a closed, controllable and highly real test environment is constructed by integrating high-fidelity driving simulation hardware, a programmable virtual driving scene, a professional edge computing voice processing unit and multi-modal synchronous data acquisition.

The present application provides a method of handling a trigger during simulation of a logical design, comprising: causing a hardware simulation tool to simulate the logical system design, the trigger associated with one or more target signals of the logical system design, the logical system design comprising a plurality of key signals, the plurality of key signals are divided into a plurality of signal groups; determining a target key signal associated with the one or more target signals in the key signals according to the description of the logic system design; determining one or more target signal groups corresponding to the target key signal in the plurality of signal groups; and reading signal values of the one or more target signal sets from the hardware simulation tool for processing the trigger.

The application discloses a kind of based on FPGA cloud platform's hardware simulation verification process implementation method, client obtains the source code file of user design, compiles integrated source code file, generates instance tree and resource occupation situation;Global instance is specified, and the instance of user design is split into small instance module;According to the instance module of splitting, the signal flow graph between different modules is generated;User is divided into different FPGA under the operation of client by following certain principle and split instance module;The attribute of signal between different FPGA is specified by client, and connection port is configured, and probe is inserted;FPGA sub-project top file is generated, and sub-project bit stream is generated by compiling, and after encryption, it is sent to cloud platform server;Trigger condition is configured in client, and cloud platform deploys running simulation program, debugs and looks waveform data and sends to client display.Satisfy the verification demand of large-scale chip design hardware simulation, and protect the intellectual property right of user.

A method for designing a time-domain non-stationary V2V MIMO communication channel emulator includes determining basic parameters for the V2V MIMO communication channel; generating a V2V 2D time-domain non-stationary communication channel environment, by using a MATLAB, that is, the numbers of the scatterers and the positions of the scatterers and the like; importing parameters generated in the previous step into a hardware simulation platform to calculate communication channel parameters for clusters, such as an angle distribution and a power distribution, writing a Verilog code for running, and eventually calculating to obtain a channel impulse response of the time-domain non-stationary V2V MIMO communication channel; and comparing with a statistical characteristic of a theoretical communication channel model, and designing an appropriate hardware diagram of a communication channel emulator. The method supports the simulation of time-domain non-stationary V2V MIMO communication channel, filling the gap in the field of communication channel emulators.

This invention discloses a method, apparatus, device, and medium for debugging a chip-based device under test (DUT) using a hardware simulation acceleration platform, relating to the field of chip design technology. The method includes: loading and connecting the DUT to a target hardware simulation acceleration platform, and setting the current clock frequency of the JTAG clock to perform debugging operations on the DUT based on the current clock frequency; during the debugging operation, determining the target number of operating cycles of the target simulation clock at a target time interval, and determining the average operating frequency of the JTAG clock based on the target time interval, the target number of operating cycles, and the current clock frequency; if the current clock frequency needs to be updated, updating the current clock frequency of the JTAG clock based on the average operating frequency to obtain the updated current clock frequency, so that debugging of the DUT can continue based on the current clock frequency. This accelerates the functional verification of chip designs on a hardware simulation acceleration platform.

The invention discloses an electronic circuit design simulation verification method and device, electronic equipment and a storage medium, and relates to the field of chip manufacturing and chip simulation verification, and the method comprises a management control module which is used for managing trigger conditions in a signal processing module and a condition judgment module; the signal processing module is used for acquiring a key signal designed by the electronic circuit to be tested through the key signal acquisition channel and sending a target key signal related to a trigger condition to the condition judgment module; and the condition judgment module is used for sending a control instruction to the hardware simulation system to control the running state of the hardware simulation system if it is determined that the target key signal meets the triggering condition. According to the technical scheme provided by the embodiment of the invention, the structural complexity of the electronic circuit design to be tested is reduced, the dynamic configuration of the trigger condition is realized, the recompilation of the whole electronic circuit design to be tested is avoided, the verification time of the circuit design is saved, and the simulation verification efficiency of the electronic circuit design to be tested is improved.

The invention relates to a deep learning acceleration core, in particular to a front-end simulation system and method for the deep learning acceleration core, and a decoding module, which decodes an external test set according to different requirements of software and hardware platforms; the hardware field recovery module is used for determining a hardware simulation starting point according to parameters input by a user, and recovering a hardware simulation field to an initialized state when full-process simulation needs to be carried out; when simulation needs to be started from the synchronization point of the sync instruction, a hardware simulation site is recovered to a position close to the sync instruction; the hardware simulation result output module is used for outputting the type of the current instruction and the corresponding program counting PC to a screen in real time when hardware simulation is carried out, and outputting a hardware simulation result; the software simulator and the result processing module are used for carrying out parameter configuration on the software simulator and outputting a software simulation result; according to the technical scheme provided by the invention, the defects of low efficiency and difficulty in quickly positioning error instructions in the prior art can be effectively overcome.

The invention discloses a simulator pre-simulation method for a hardware simulation scene, and relates to the technical field of simulator pre-simulation, and the method comprises the following steps: S1, constructing a performance mapping relation model for a simulator; s2, on the basis of the performance mapping relation model, analyzing the multi-thread parallel issuing performance, and generating multi-thread prediction performance; and S3, receiving an original instruction stream, and performing heterogeneous scene optimization in combination with multi-thread prediction performance to complete pre-simulation. According to the method, rapid and accurate simulator estimation facing a hardware simulation scene is realized, the problems of long hardware simulation time, difficulty in resource planning, long performance optimization period and the like are effectively solved, compared with a traditional method, the working efficiency is greatly improved, the method has good expansibility, and the method is not only suitable for mapping between NEMU and lego-sim, but also suitable for mapping between NEMU and lego-sim. And the method can be expanded to other simulator platforms and has a wide application prospect.

This application provides a chip functional verification method, apparatus, electronic device, and storage medium, relating to the field of chip design and manufacturing technology. The method includes: decomposing the design under test (DUT) into multiple first sub-modules; and decomposing a reference model of the DUT into multiple second sub-modules corresponding to the functions of the first sub-modules; simultaneously using the output of the current first sub-module as the input of the next first sub-module downstream of the data stream and the input of the second sub-module corresponding to the next first sub-module; and determining the functional verification result of the DUT based on the comparison results of the outputs of each first sub-module and the corresponding second sub-modules. The method and apparatus provided in this application synchronously decompose the DUT and the reference model and establish a co-simulation mechanism that drives the reference model execution using hardware simulation results. This can quickly and accurately locate chip design defects, improving chip verification efficiency and debugging convenience.

The application discloses a GPU cluster silicon pre-verification method, a simulation platform, a storage medium and a program product. When the silicon pre-verification of the GPU cluster is performed, at least one network card is mapped as a simulation GPU card, and all network cards and at least one virtual GPU card generated by a hardware simulator are respectively connected with a switch to control each network card to send simulation traffic to the switch according to a preset message sending rule. Based on a target port in the switch, messages sent by all virtual GPU cards are mirrored to at least one target network card, and analysis software is used to capture and analyze the mirrored messages received by the target network card. According to the embodiment of the application, a large-scale GPU interconnection scene can be quickly built through a common PC network card, convenient message debugging is realized, and the efficiency and safety of the silicon pre-verification are improved.

This application discloses a data transmission performance prediction method, apparatus, device, and storage medium, belonging to the field of computer technology. The method includes: dividing the data to be transmitted into a data block set according to the storage capacity of the target storage unit and the data information of the data to be transmitted in the source storage unit, following the scheduling mechanism of the data access unit; transforming the expression of the data block set to obtain a target dataset, so that the expression of the target dataset is applicable to transform analysis; performing transform analysis on the target dataset to obtain the step size of the source shape, the step size of the target shape, and the transpose type; and using a hardware simulation model of the data access unit, based on the hardware characteristics of the data access unit occupying bandwidth when performing transpose and shape transformation steps, predicting the data transmission performance under the scheduling mechanism according to the step size of the source shape, the step size of the target shape, the original bandwidth, and the transpose type, thereby improving the accuracy of the performance prediction results.

The invention discloses a printing method and device of chip software and hardware simulation character strings, equipment and a medium, and relates to the technical field of chip embedded simulation, and the printing method of the chip software and hardware simulation character strings comprises the following steps that S10, a preset printing function is executed in response to a printing instruction, obtaining a character string needing to be printed according to the obtained character string address; wherein the preset printing function is edited based on a character string address; and step S20, printing the obtained character string. According to the method, the original printing function based on one-by-one printing of the single characters is modified into the printing function based on the character string address, and when the instruction of printing the character string is executed, the time required for printing can be shortened, so that the simulation time can be saved, and the simulation efficiency can be improved. In addition, too many resources of the chip CPU are not occupied when the serial port is written.

A method of verifying a logic circuit design by a hardware emulation system, includes, in part, receiving a netlist of the logic circuit design configured to operate in response to positive edges of a first clock signal, and transforming each of a first multitude of flip-flops disposed in the logic circuit design to a dual-enable flip-flop configured to operate in response to positive edges of a second clock signal thereby to generate a transformed logic circuit design. The state of the logic circuit design after 2k cycles of the first clock is the same as a state of the transformed logic circuit design after k cycles of the second clock.