7 results about "Hardware emulation" patented technology

This invention discloses a method, apparatus, device, and medium for debugging a chip-based device under test (DUT) using a hardware simulation acceleration platform, relating to the field of chip design technology. The method includes: loading and connecting the DUT to a target hardware simulation acceleration platform, and setting the current clock frequency of the JTAG clock to perform debugging operations on the DUT based on the current clock frequency; during the debugging operation, determining the target number of operating cycles of the target simulation clock at a target time interval, and determining the average operating frequency of the JTAG clock based on the target time interval, the target number of operating cycles, and the current clock frequency; if the current clock frequency needs to be updated, updating the current clock frequency of the JTAG clock based on the average operating frequency to obtain the updated current clock frequency, so that debugging of the DUT can continue based on the current clock frequency. This accelerates the functional verification of chip designs on a hardware simulation acceleration platform.

This application provides a chip functional verification method, apparatus, electronic device, and storage medium, relating to the field of chip design and manufacturing technology. The method includes: decomposing the design under test (DUT) into multiple first sub-modules; and decomposing a reference model of the DUT into multiple second sub-modules corresponding to the functions of the first sub-modules; simultaneously using the output of the current first sub-module as the input of the next first sub-module downstream of the data stream and the input of the second sub-module corresponding to the next first sub-module; and determining the functional verification result of the DUT based on the comparison results of the outputs of each first sub-module and the corresponding second sub-modules. The method and apparatus provided in this application synchronously decompose the DUT and the reference model and establish a co-simulation mechanism that drives the reference model execution using hardware simulation results. This can quickly and accurately locate chip design defects, improving chip verification efficiency and debugging convenience.

This application discloses a data transmission performance prediction method, apparatus, device, and storage medium, belonging to the field of computer technology. The method includes: dividing the data to be transmitted into a data block set according to the storage capacity of the target storage unit and the data information of the data to be transmitted in the source storage unit, following the scheduling mechanism of the data access unit; transforming the expression of the data block set to obtain a target dataset, so that the expression of the target dataset is applicable to transform analysis; performing transform analysis on the target dataset to obtain the step size of the source shape, the step size of the target shape, and the transpose type; and using a hardware simulation model of the data access unit, based on the hardware characteristics of the data access unit occupying bandwidth when performing transpose and shape transformation steps, predicting the data transmission performance under the scheduling mechanism according to the step size of the source shape, the step size of the target shape, the original bandwidth, and the transpose type, thereby improving the accuracy of the performance prediction results.

A method of verifying a logic circuit design by a hardware emulation system, includes, in part, receiving a netlist of the logic circuit design configured to operate in response to positive edges of a first clock signal, and transforming each of a first multitude of flip-flops disposed in the logic circuit design to a dual-enable flip-flop configured to operate in response to positive edges of a second clock signal thereby to generate a transformed logic circuit design. The state of the logic circuit design after 2k cycles of the first clock is the same as a state of the transformed logic circuit design after k cycles of the second clock.

The present application relates to chip design technical field, especially to a waveform data acquisition method, electronic equipment and storage medium, it is through the target node of user specified capture each processing unit target data and compress storage to cache, in each device cycle target data in the cache is removed to memory;Wherein, the step of capturing the target data of the fth processing unit and compressing storage to cache includes: according to the target node, the data stream of the fth processing unit continuous output is filtered to obtain the data block including target node data;While the data block of cache changes, the change flag position of the data block of data change is valid, and the change flag position of the data block of no change is invalid.It not only allows the user to specify a large number of target nodes or change target nodes, without recompilation, improves the debugging efficiency;And reduce the occupied cache and memory space, improve the hardware simulation speed.