Design method of built-in parallel two-dimensional discrete wavelet conversion VLSI structure

A two-dimensional discrete wavelet and structure design technology, applied in computing, special data processing applications, instruments, etc., can solve the problems of limiting chip processing data speed, increasing hardware resource consumption and chip cost, reducing hardware utilization, etc., to achieve Cost savings, increased utilization and processing speed, and reduced computation

Inactive Publication Date: 2003-10-15
XI AN JIAOTONG UNIV
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Problems solved by technology

Among the existing 2-D DWT chip structures, most of the structures have exactly the same structural design for the two stages of fast discrete wavelet transform (row filtering and column filtering). Although this reduces the control complexity, the middle of the row filteri

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  • Design method of built-in parallel two-dimensional discrete wavelet conversion VLSI structure
  • Design method of built-in parallel two-dimensional discrete wavelet conversion VLSI structure
  • Design method of built-in parallel two-dimensional discrete wavelet conversion VLSI structure

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Embodiment Construction

[0019] The present invention will be described in further detail below in conjunction with drawings and embodiments, but the present invention is not limited to this embodiment.

[0020] According to the technical solution of the present invention, the inventor provides the embodiments of the present invention. In this embodiment, a set of biorthogonal wavelet filters in the JPEG2000 standard——DAUBECHIES 9 / 7 biorthogonal wavelets are used.

[0021] In this embodiment, first, the multiplication operation in the filter is implemented with a shift register and an adder through the general "shift-add" technique. In the operation process, fixed-point calculation is adopted, the last 13 digits are decimals, and the data width is 24 digits.

[0022] Through the "shift-add" technique, this embodiment changes the multiplication into a shift-add operation. In view of the fact that the filter coefficients of the two-dimensional discrete wavelet transform are fixed, this makes the desig...

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Abstract

The VLSI structure design method includes shift adding technology to converting the multiplication operation in the filter into shift register and adder operation to reduce the operation amount save hardware spending greatly; buffering technology to connect row and line filters for concurrent performing to save memory space; delay register technology for streamline processing to speed hardware processing and raise hardware utilization; and united symmetrical expanding technology to raise the versatility of the present invention. The present invention is one efficient 2D DWT hardware scheme with several advantages. Through the optimized design of row filter and line filter for 2D discrete wavelet conversion, the hardware utilization is made to reach 100 %, there are two outputs within one work clock, parallel processing is realized without increasing hardware spending, and the obtained hardware structure is simple and easy to realize with VLSI.

Description

1. Technical field [0001] The invention belongs to the technical field of VLSI design. Specifically, it involves designing an inherently parallel and efficient VLSI structure design method based on two-dimensional discrete wavelet transform of lifting algorithm in the implementation of JPEG2000 hardware. 2. Background technology [0002] The 2D-DWT hardware structure has good time-frequency analysis characteristics so that it can be applied in many practical systems, such as Jpeg2000 standard encoding system and video processing, etc. Considering the requirements of speed and area, it is necessary to use a chip to realize the compression system. Among the existing 2-D DWT chip structures, most of the structures have exactly the same structural design for the two stages of fast discrete wavelet transform (row filtering and column filtering). Although this reduces the control complexity, the middle of the row filtering The storage of the results requires a large amount of sto...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 兰旭光郑南宁周宁梅魁志
Owner XI AN JIAOTONG UNIV
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