Design method of built-in parallel two-dimensional discrete wavelet conversion VLSI structure

Abstract

The VLSI structure design method includes shift adding technology to converting the multiplication operation in the filter into shift register and adder operation to reduce the operation amount save hardware spending greatly; buffering technology to connect row and line filters for concurrent performing to save memory space; delay register technology for streamline processing to speed hardware processing and raise hardware utilization; and united symmetrical expanding technology to raise the versatility of the present invention. The present invention is one efficient 2D DWT hardware scheme with several advantages. Through the optimized design of row filter and line filter for 2D discrete wavelet conversion, the hardware utilization is made to reach 100 %, there are two outputs within one work clock, parallel processing is realized without increasing hardware spending, and the obtained hardware structure is simple and easy to realize with VLSI.

Description

1. Technical field [0001] The invention belongs to the technical field of VLSI design. Specifically, it involves designing an inherently parallel and efficient VLSI structure design method based on two-dimensional discrete wavelet transform of lifting algorithm in the implementation of JPEG2000 hardware. 2. Background technology [0002] The 2D-DWT hardware structure has good time-frequency analysis characteristics so that it can be applied in many practical systems, such as Jpeg2000 standard encoding system and video processing, etc. Considering the requirements of speed and area, it is necessary to use a chip to realize the compression system. Among the existing 2-D DWT chip structures, most of the structures have exactly the same structural design for the two stages of fast discrete wavelet transform (row filtering and column filtering). Although this reduces the control complexity, the middle of the row filtering The storage of the results requires a large amount of sto...

AI Technical Summary

Problems solved by technology

Among the existing 2-D DWT chip structures, most of the structures have exactly the same structural design for the two stages of fast discrete wavelet transform (row filtering and column filtering). Although this reduces the control complexity, the middle of the row filtering The storage of the results requires a large amount of storage space, which not only reduces the utilization rate of the hardware, but also increases the consumption of hardware resources and the cost of the chip, which limits the speed at which the chip can process data.

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