43 results about "Interconnect technology" patented technology

According to the storage and calculation integrated chip architecture, the chip stacking packaging structure and the terminal equipment, physical tight coupling of storage and calculation is realized through the 3D stacking design of the first storage unit and the logic calculation unit, the problem of physical separation of traditional storage and calculation is solved, the data carrying distance and the cross-chip communication overhead are remarkably reduced, and the communication efficiency is improved. And the chip area and the packaging process complexity are reduced, and the application scenarios of end-side artificial intelligence reasoning and mass data reading and writing are supported. According to the storage and calculation integrated chip architecture, the first storage unit and the logic calculation unit are directly interconnected through the vertical interconnection technology, the data access delay is reduced, the requirement of end side equipment for low delay is met, and the energy efficiency ratio of the storage and calculation integrated chip architecture is remarkably reduced.

Configurations are disclosed for multi-wavelength optical devices and systems. In particular, multi-wavelength optical devices that include separate chips optically connected via phonic wire bonds. The disclosed configurations can utilize photonic wire bond interconnects and photonic wire bond interconnection techniques, which may facilitate low-cost implementation of wavelength division multiplexed optical systems.

The invention relates to the technical field of semiconductor copper interconnection, in particular to a hole filling method of a copper interconnection semiconductor cooler, which comprises the following steps of: performing multi-stage chemical cleaning treatment on a semiconductor substrate after laser drilling, removing dirt on the surface of the substrate, coarsening the surface of the substrate to increase binding force and removing residual slag at a hole after drilling; the influence on seed layer sputtering in subsequent holes caused by slag accumulation at the hole opening is avoided; and meanwhile, three-step electroplating of the initial copper layer, through hole filling and orifice and surface leveling are adopted, so that cavity-free hole filling and surface nanoscale leveling are realized, and the final product yield is improved.

Presented herein are techniques through which modular architectures and systems may be implemented for superconducting (SC) quantum processing elements or chips utilizing photonic interconnects. In one instance, an SC processing element is provided that includes a plurality of interconnected qubits, wherein a first qubit of the plurality of interconnected qubits is interconnected with a first microwave-optical transducer. In one instance, a system is provided that includes a first SC processing element comprising a first plurality of interconnected qubits, wherein a first microwave-optical transducer is interconnected with a first qubit of the first plurality of interconnected qubits; a second SC processing element comprising a second plurality of interconnected qubits, wherein a second microwave-optical transducer is interconnected with a first qubit of the second plurality of interconnected qubits; and an optical network interconnecting the first microwave-optical transducer and the second microwave-optical transducer.

The present invention provides a three-dimensional integrated system of compatible chips and a manufacturing method thereof, wherein at least one functional chip is expanded to form an extended chip including the functional chip and a peripheral pad, and the pad of the functional chip is electrically led out to the peripheral pad by rewiring. Based on the alignment and bonding of the two extended chips corresponding to the peripheral pads, or based on the alignment and bonding of a functional chip and an extended chip, the electrical connection and three-dimensional integration between the two functional chips are simply and efficiently completed, and the integrated connection between the two independent functional chips is realized based on the peripheral extended pad. Each functional chip can be manufactured using its own independent process system, and each functional chip can work independently to ensure optimal performance. The process compatibility with the functional chip is strong and the usage scenarios are wide. At the same time, the three-dimensional integration and electrical connection are realized based on the peripheral extended pad. Compared with the complex silicon through-silicon via integrated interconnection technology, the manufacturing process is relatively simple, the technical difficulty is low, and the yield rate is high.

The present application discloses a cable function detection method and device, which relate to the field of high-speed electronic interconnection technology, focusing on cables such as Slimline and MCIO used in servers, constructing a simulated connection mapping for testing the expected cable to be tested, initializing a connection mapping dictionary for recording actual detection results, sending a detection signal to each core at one end in sequence, and receiving a response signal at the other end, and recording and outputting the detection result mapping relationship, thereby solving the problems of the existing detection system having a single function and being unable to evaluate the true electrical performance of the cable, the problem of difficulty in batch cable quality control, and the problem of complex cables being unable to quickly replace detection parameters and having high switching costs, thereby reducing manual insertion errors and misjudgments, improving test efficiency and management capabilities, and facilitating maintenance and adaptation of cables of different specifications. The application is suitable for multiple scenarios such as R&D verification, production line sampling, and after-sales inspection.

This invention discloses a multi-objective prediction method for wirebond thermal fatigue life and electrical performance, belonging to the field of microwave interconnect technology. The method includes: determining the physical and structural parameters of the wirebond interconnect structure; obtaining a mathematical description of the wirebond morphology; establishing a thermal analysis model and a structural-electromagnetic analysis model for the wirebond interconnect structure; designing comprehensive experiments and obtaining various performance indicators; establishing a mapping relationship model from wire geometry parameters to various performance indicators; establishing a thermal fatigue life prediction model and completing reliability life prediction. This method can be used to accurately parameterize wirebond interconnect structural models, rapidly achieve multi-objective prediction of wirebond thermal fatigue life and electrical performance, and guide the structural design and optimization of wirebond packages.

The embodiments of the present disclosure provide a board and a server, which relates to the technical field of processor board card interconnection. By arranging the first internal connectors in the second internal connector configuration area and the second internal connectors in the first internal connector configuration area; the first processor is electrically connected to the first internal connectors through the first circuit, and the second processor is electrically connected to the second internal connectors through the second circuit, and the first circuit and the second circuit are arranged in an intersecting way. Based on the wiring design of the board of the embodiments of the present disclosure for multi-board interconnection, the complexity of the cable topology structure in the board group may be effectively simplified, thereby improving the maintenance efficiency of multi-card interconnection, and reducing the construction difficulty and maintenance cost.

The utility model relates to the field of electronic components and interconnection technology discloses a kind of quick docking structure of pin and female header with guide bevel, including female seat, pin seat, mounting structure, rotating structure, fixed structure, guide positioning structure and connecting structure, the Chinese character-shaped mounting plate of mounting structure collocates mounting hole, it is convenient to flexibly install, guide positioning structure is accurately guided butt joint by positioning hole one, positioning rod and positioning hole two, the pin foot of connecting structure is equipped with guide bevel, easy to insert female seat jack, realize reliable electrical connection, rotating and fixed structure cooperate, utilize fixed seat, fixed rod, fixed groove, connecting block and bolt to enhance positioning accuracy and connection stability, compared with traditional pin and female header, the structure effectively solves the problems, such as low docking efficiency, poor positioning accuracy, improves electronic equipment assembly efficiency and operating reliability, suitable for the quick assembly and frequent plugging scene of multiple electronic equipment.

The application discloses a three-dimensional integrated packaging structure based on a dielectric integrated suspended line, which comprises N layers of dielectric plates covered with metal on both sides; the N layers of dielectric plates are stacked from bottom to top; the dielectric plates of any one or any multiple adjacent layers from the 2nd layer to the N-1th layer are patterned and hollowed to form at least one air cavity; metalized through holes are formed on the 1st layer to the Nth layer to form an electric wall around the air cavity; the 1st layer and the Nth layer together with the formed electric wall constitute an electromagnetic shielding cavity; the 2nd layer to the N-1th layer are electrically connected through a three-dimensional vertical interconnection technology; and one or more functional devices are arranged in each air cavity. The application can realize the collaborative design of functional devices, system circuits and packaging, reduce the influence of packaging on the performance of circuits, reduce the mutual interference between functional devices, facilitate individual debugging, reduce transmission loss, be favorable for realizing high-speed data transmission and improve system reliability.

The invention relates to the technical field of circuit board manufacturing, and provides a circuit board manufacturing method and a circuit board, and the circuit board manufacturing method comprises the steps: providing a first sub-board, a connecting board and a second sub-board; an anti-oxidation layer is arranged on the surface of the first bonding pad of the first sub-board and / or the surface of the second bonding pad of the second sub-board; through holes are formed in the positions, corresponding to the first bonding pad of the first daughter board and the second bonding pad of the second daughter board, of the connecting board, and the through holes are filled with conducting media; and the first daughter board, the connecting board and the second daughter board are stacked and laminated in sequence, so that the first bonding pad of the first daughter board and the second bonding pad of the second daughter board are electrically conducted through the conductive medium. According to the circuit board manufacturing method, the anti-oxidation layer is used for protecting the surface of the bonding pad, so that the surface of the bonding pad is not easy to oxidize, the surface of the bonding pad and the conducting medium form an IMC layer, the binding force of the surface of the bonding pad and the conducting medium is improved, and the interconnection reliability of the circuit board adopting the Z-direction interconnection technology is improved.

The invention discloses a heat dissipation structure based on combination of vertical interconnection of a glass substrate chip and a liquid metal shielding case, the structure is mainly composed of a glass substrate (1), a heat source chip (2), the liquid metal shielding case (3), a metal heat conduction rod (4), a micro-channel (5) and a TGV through hole (8), and the TGV refers to a three-dimensional interconnection (TGV) technology based on glass through hole manufacturing. A heat dissipation structure based on combination of glass substrate chip vertical interconnection and a liquid metal shielding cover is mainly characterized in that a heat source chip (2) is vertically interconnected on a glass substrate (1) through a TGV technology, the liquid metal shielding cover (3) is installed on the heat source chip (2), and heat conduction silicone grease needs to be filled between the heat source chip and the liquid metal shielding cover to reduce heat resistance. A cavity for containing liquid metal (3) is formed in the liquid metal shielding cover, electromagnetic signals can be shielded, efficient heat dissipation of the heat source chip (2) can be achieved, the metal heat conduction rods (4) are machined through the metalized TGV through holes, effective heat transfer can be conducted on the liquid metal, heat exchange media in the micro-channels (5) in the glass substrate can conduct convective heat exchange on the metal heat conduction rods, and the heat conduction efficiency of the heat source chip (2) is improved. Heat generated by the heat source chip (2) is effectively conducted. The temperature of the heat source chip can be obviously reduced, the low heat dissipation efficiency caused by the low heat conductivity of the glass substrate is improved, the main heat conduction process comprises the heat source chip (2), the liquid metal shielding cover (3), the metal heat conduction rod (4), the internal heat exchange medium of the micro-channel (5) and the outside, the temperature distribution of the structure in the vertical direction is effectively improved, and the heat dissipation efficiency is improved. The heat dissipation limit of the structure is improved, and the service life of the chip is prolonged. The heat dissipation structure is compact in structure, space-saving and good in heat dissipation capability, is an efficient heat dissipation structure, and has a better application prospect in the heat dissipation field of high-heating chips.

This invention discloses a solderless bonding method for interconnecting flexible micro-LEDs with flexible circuits, belonging to the field of flexible Micro-LED display interconnect technology. The method includes fabricating three layers of metal bumps on chip electrodes, forming a composition-matched receiving layer on a flexible substrate, aligning and bonding them after atomic-level cleaning, and achieving solid-state diffusion bonding under low temperature and low pressure to form a stable intermetallic compound interface. This application effectively solves the problems of thermal stress mismatch, interface delamination, and unstable contact resistance under bending caused by solder bonding, improving the reliability and mass production compatibility of high-density flexible Micro-LED devices.

The application relates to the technical field of optical fiber interconnection, and provides a chip supporting efficient interconnection of multiple heterogeneous hollow core optical fibers and a design method. The chip comprises a first grating, a second grating and a connecting waveguide; the first grating is used for coupling with a first hollow core optical fiber, the second grating is used for coupling with a second hollow core optical fiber; and the connecting waveguide is used for connecting the first grating and the second grating. The application provides a technical scheme for realizing the coupling of corresponding hollow core optical fibers through corresponding gratings, and realizing the interconnection of the hollow core optical fibers through the connection between the gratings and the connecting waveguide. Since the grating and the connecting waveguide are both designed based on a silicon-based chip, the preparation difficulty is low, and batch production is possible.

The present disclosure relates to optical interconnect technology between computing modules, and particularly to a computing module that includes an optical interconnect unit. According to one aspect of the present disclosure, there is provided a computing module, the computing module comprising: a substrate; a data processing unit disposed on a surface of or inside the substrate; a signal switching unit disposed on the surface of or inside the substrate; an optical interconnect unit; and an optical waveguide. In the computing module, optical signal transmission between the signal switching unit and the optical interconnect unit is implemented via the optical waveguide, the optical interconnect unit comprising: a collimating lens array in optical connection with the optical waveguide; a control unit disposed near the collimating lens array; and a microcontroller disposed on the surface of or inside the substrate, wherein the microcontroller is configured to, based on an optical signal intensity measured at the signal switching unit, adjust a refractive index or a position of the collimating lens array via the control unit to improve an optical coupling efficiency between the optical waveguide and the optical interconnect unit.

The utility model relates to the technical field of circuit board interconnection, and discloses a multilayer integrated circuit board interconnection device which comprises a base, a placing plate is arranged on one side of the outer surface of the base, a support is arranged on one side of the outer surface of the base, a device plate is arranged on one side of the outer surface of the support, and a threaded ring is arranged on one side of the outer surface of the device plate. A threaded rod is arranged on one side of the outer surface of the threaded ring, a connecting box is arranged at one end of the threaded rod, a device pipe is arranged in the connecting box, a connecting rod is arranged at one end of the device pipe, a fixing block is arranged at one end of the connecting rod, an auxiliary plate is arranged in the connecting box, and an auxiliary pipe is arranged on one side of the outer surface of the auxiliary plate. According to the device, the poke rod is arranged in the device, the poke rod is fixedly connected with the inserting rod, when the poke rod moves up and down, the inserting rod moves up and down, when the inserting rod is disconnected with the connecting rod, the fixing block can be taken down, and the effect of replacing the fixing block is achieved.

The invention discloses a cable function detection method and device, relates to the technical field of high-speed electronic interconnection, focuses on cables such as Slimline and MCIO used for a server, constructs simulation connection mapping used for testing an expected to-be-detected cable, initializes a connection mapping dictionary used for recording an actual detection result, and determines the function of the to-be-detected cable according to the connection mapping dictionary. Detection signals are sequentially sent to each wire core at one end, response signals are received at the other end, and a detection result mapping relation is recorded and output, so that the problems that an existing detection system is single in function and cannot evaluate the real electrical performance of the cable and the quality of batch cables is difficult to control are solved; the problems that detection parameters of complex cables cannot be rapidly replaced and the switching cost is high are solved, the effects of reducing manual insertion errors and misjudgment, improving the test efficiency and management capability and facilitating maintenance and adaptation of cables of different specifications are achieved, and the cable detection device is suitable for multi-scene application such as research and development verification, production line sampling inspection and after-sales investigation.

The invention relates to the technical field of electronic packaging advanced interconnection, in particular to a nano twin crystal silver-copper alloy material and a preparation method thereof. The preparation method comprises the following steps: S1, polishing the surface of the substrate until Ra is less than or equal to 0.04 mu m; s2, carrying out ultrasonic cleaning and drying on the substrate; s3, selecting a silver target and a copper target as target materials, putting the substrate and the target materials into magnetron sputtering equipment, vacuumizing, introducing argon into a vacuum chamber, applying a direct-current high-voltage electric field, and carrying out direct-current magnetron co-sputtering deposition under the conditions that the incident angle is 0 degree, the substrate and the target materials are spaced, the temperature of the substrate is 25 DEG C, the argon flow is 30-50 sccm, the argon pressure is 6-9 mTorr and the vacuum degree of a sputtering chamber before sputtering is less than 1 * 105 Pa; the deposition time is 60 to 90 minutes. The silver-copper alloy material is good in structure uniformity, the silver-copper alloy components are adjustable, the thickness is controllable, bias voltage does not need to be applied, and the physical vapor deposition technology is adopted to be compatible with the integrated circuit manufacturing process.

The invention relates to the technical field of memristor array design, and discloses a 3D stacked memristor array design method for high-energy-efficiency AI calculation, and the method comprises the following steps: S1, constructing a layered heterogeneous 3D stacked architecture which comprises the physical isolation and dynamic reconstruction of a storage layer, a calculation layer and a control layer; s2, establishing a coupling relation model of a temperature field and memristor resistance state drift based on a dynamic thermal-electric cooperative regulation and control algorithm, and optimizing voltage pulse parameters in real time; s3, dynamically distributing mixed precision pulses according to the sparse characteristic of the AI model through sparse perception adaptive gating; and S4, deploying a hardware acceleration unit in a control layer, and realizing thermal-electric parameter calculation and real-time coding transmission of a regulation and control instruction. By adopting the technical scheme of layered heterogeneous 3D stacking architecture and hybrid bonding vertical interconnection, the effect of data near processing and transmission loss collaborative optimization is achieved, and the problems of extra energy consumption and delay caused by cross-layer data handling are solved.

Exemplary embodiments are disclosed of EMI absorbers that are operable for suppressing and / or absorbing EMI noise at relatively high frequencies for high-speed cables, e. g., cables for interconnect from chip to board, integrated circuit (IC) package to board, input / output (I / O) panel to board, board to board, module to board, subsystem to board, supporting high-speed interconnect technology standards, such as Peripheral Component Interconnect Express (PCIe) Gen 5 / 6 / 7, etc. and Computer Express Link (CXL) 3.1, etc. In exemplary embodiments, the EMI absorber comprises a moldable thermoplastic EMI absorber configured to be operable for suppressing and / or absorbing EMI noise from a cable or another component including frequencies from 5 gigahertz to 70 gigahertz when the EMI absorber is positioned on a portion of the cable or another component, e. g., when the EMI absorber entirely and / or continuously surrounds (e. g., is disposed 360 degrees around, etc.) the portion of the cable or another component.

The present invention relates primarily to the field of 3D interconnection technologies for microelectronics, but also to any application requiring high wettability contrast on the micrometer scale. The proposed method makes it possible to manufacture a wafer (1) having a main surface (10) with solid regions (101) and micro- or nanostructured regions (102) having a wettability contrast between them of greater than 90°, preferably greater than 120°, each structured region (102) extending around the solid region (101), the wafer comprising a substrate (11) having a first level (111) mainly made of a semiconductor material and a second level (112) mainly made of a dielectric material, the solid regions and each structured region being formed on the second level of the substrate, each structured region having a plurality of protrusions (131) mainly made of said dielectric material, the wafer being such that the protrusions have faceted edges.

The invention discloses a TGV / TSV low parasitic inductance and capacitance structure and a manufacturing method thereof, and belongs to the technical field of TGV / TSV. Through the innovative structural design and manufacturing method, the parasitic inductance and capacitance of the TGV and the TSV are effectively reduced, the signal transmission quality and efficiency are improved, and the requirements of high-speed and high-performance chips for the interconnection technology are met.

The invention belongs to the technical field of sensor open system architecture (SOSA), and discloses a universal signal processor of a software defined bus and an interface protocol. The interface and the bus of the signal processor have the characteristic of software definable interconnection, are not limited to a certain fixed interface and bus, and can be suitable for different purposes and purposes. System interconnection is supported in a software-defined hardware mode, software can be defined as a single protocol needed for use of a certain device, bridging between different protocols and generation of multiple protocols can be achieved based on software-defined interconnection technology genes, hybrid interconnection of heterogeneous protocols and user-defined protocols is supported, and the system interconnection efficiency is improved. And a new software-defined interconnection equipment system is created, is flexible and variable, and provides technical support for multifunctional integrated back-end processing.

Technologies for radiofrequency optimized interconnects for a quantum processor are disclosed. In the illustrative embodiment, signals are carried in coplanar waveguides on a surface of a quantum processor die. A ground ring surrounds the signals and is connected to the ground conductors of each coplanar waveguide. Wire bonds connect the ground ring to a ground of a circuit board. The wire bonds provide both an electrical connection from the quantum processor die to the circuit board as well as increased thermal coupling between the quantum processor die and the circuit board, increasing cooling of the quantum processor die.

The invention discloses an aerospace camera controller main and standby circuit board isomorphic redundancy design method based on an inter-board interconnection technology, and solves the problems of large space size, high design cost, long development period and the like of main and standby single-machine circuit boards in the prior art. According to the camera controller, the inter-board interconnection technology is adopted, the main circuit board and the standby circuit board of the camera controller are integrated into a single circuit board structure through the inter-board connector in a specific form and the optimized layout of the inter-board connector on the circuit board in combination with an isomorphic design concept. According to the design, cross control, collection and combined transmission of signals of the main board and the standby board are achieved through interconnection of the connectors between the boards, the signal switching and combining functions of a traditional redundant framework are achieved, the number of external connectors is reduced, the complexity of transmission cables is simplified, the structural size is reduced, the single-machine cost is reduced, and the development period is shortened. According to the isomorphic design, the fault-tolerant capability of spaceflight-level equipment is remarkably improved while the reliability of the system is improved, and the method has great engineering design reference value.

A semiconductor device assembly including a first module having one or more memory arrays, each of the one or more memory arrays being connected to a plurality of landing pads of the first module; and a second module having complementary metal-oxide-semiconductor devices, the second module including a plurality of socket shallow trench isolation (STI) regions disposed in a substrate of the second module, a plurality of metal routing layers connected to corresponding CMOS devices, a plurality of a first type of via contacts each being connected to a corresponding one of the plurality of metal routing layers, and a plurality of a second type of via contacts each being connected to a corresponding one of the plurality of landing pads of the first module, wherein the plurality of the first type of via contacts and the plurality of the second via contacts pass through the plurality of socket STI regions.

This disclosure provides a shared memory interconnect device, arbitration method, and arbitration circuit, relating to the field of integrated circuit interconnect technology. The implementation scheme is as follows: a hierarchical interconnect network includes an outer routing network and an inner switching network. The outer routing network includes a multi-level switching network composed of multiple butterfly switching units, used to route data stream packets from input ports to multiple subgroups of the inner switching network. The inner switching network includes multiple crossbar switching modules for performing local non-blocking switching. An arbitration module maintains the weights of each input port and determines the arbitration result based on the weights between conflicting ports. When arbitration fails, the weight of the corresponding port is incremented by a preset increment. When arbitration succeeds, the weight of the corresponding port is restored to its initial value. The arbitration result of each port is determined by cascading the arbitration status between conflicting ports, which can significantly reduce hardware area overhead while ensuring local bandwidth and low latency.

Aspects of the disclosure are directed to flexible digital audio system interconnectivity. In accordance with one aspect, the disclosure includes assigning a plurality of virtual transport link managers to a plurality of transport links according to a control plane allocation and a data plane allocation; and transporting control plane information and data plane information over the plurality of transport links to a plurality of audio peripherals using the plurality of virtual transport link managers. In one example, the method further includes interconnecting the plurality of transport links to the plurality of audio peripherals with the control plane allocation and with the data plane allocation to form an interconnection.

A hybrid core-shell material preform of micron-sized Ag, micron-sized In, and micron-sized Cu@In, along with its preparation method and applications, belongs to the field of electronic packaging micro-interconnect technology. The specific method involves: preparing a micron-sized Cu@In core-shell material via chemical plating, and mixing it with micron-sized In particles and micron-sized Ag particles to obtain a hybrid core-shell material preform of micron-sized Ag, micron-sized In, and micron-sized Cu@In. The hybrid core-shell material preform is placed on a substrate, and the chip, preform, and substrate are assembled into a sandwich structure to obtain an integrated device. The integrated device is then connected under a certain pressure to obtain an interconnect device. This invention can be well applied in the fields of semiconductor device manufacturing, microelectronic packaging, and power electronic packaging.

The application discloses a PCIe device and a control method thereof, and belongs to the technical field of computer architecture, heterogeneous computing and high-speed peripheral device interconnection. The PCIe device control method comprises the following steps: communicating with a host device through a PCIe interface module, receiving a working mode switching instruction sent by the host device, wherein the working mode switching instruction comprises a target working mode; a management module records the target working mode, and outputs a ready state to the host device through a command interaction module after completing switching preparation corresponding to the target working mode; after the host device receives the ready state, PCIe function level reset is triggered; when the PCIe interface module detects PCIe function level reset, reset indication information is provided to the management module; and the management module configures an access strategy of a storage access control module according to the target working mode in response to the reset indication information, and starts, stops or resets a task processing module through an enable-stop control module. The application can support dynamic switching of the working mode of the PCIe device.