7 results about "Interconnect technology" patented technology

The application relates to the technical field of optical fiber interconnection, and provides a chip supporting efficient interconnection of multiple heterogeneous hollow core optical fibers and a design method. The chip comprises a first grating, a second grating and a connecting waveguide; the first grating is used for coupling with a first hollow core optical fiber, the second grating is used for coupling with a second hollow core optical fiber; and the connecting waveguide is used for connecting the first grating and the second grating. The application provides a technical scheme for realizing the coupling of corresponding hollow core optical fibers through corresponding gratings, and realizing the interconnection of the hollow core optical fibers through the connection between the gratings and the connecting waveguide. Since the grating and the connecting waveguide are both designed based on a silicon-based chip, the preparation difficulty is low, and batch production is possible.

A semiconductor device assembly including a first module having one or more memory arrays, each of the one or more memory arrays being connected to a plurality of landing pads of the first module; and a second module having complementary metal-oxide-semiconductor devices, the second module including a plurality of socket shallow trench isolation (STI) regions disposed in a substrate of the second module, a plurality of metal routing layers connected to corresponding CMOS devices, a plurality of a first type of via contacts each being connected to a corresponding one of the plurality of metal routing layers, and a plurality of a second type of via contacts each being connected to a corresponding one of the plurality of landing pads of the first module, wherein the plurality of the first type of via contacts and the plurality of the second via contacts pass through the plurality of socket STI regions.

This disclosure provides a shared memory interconnect device, arbitration method, and arbitration circuit, relating to the field of integrated circuit interconnect technology. The implementation scheme is as follows: a hierarchical interconnect network includes an outer routing network and an inner switching network. The outer routing network includes a multi-level switching network composed of multiple butterfly switching units, used to route data stream packets from input ports to multiple subgroups of the inner switching network. The inner switching network includes multiple crossbar switching modules for performing local non-blocking switching. An arbitration module maintains the weights of each input port and determines the arbitration result based on the weights between conflicting ports. When arbitration fails, the weight of the corresponding port is incremented by a preset increment. When arbitration succeeds, the weight of the corresponding port is restored to its initial value. The arbitration result of each port is determined by cascading the arbitration status between conflicting ports, which can significantly reduce hardware area overhead while ensuring local bandwidth and low latency.

A seed layer for deep vias in glass and its preparation method are disclosed, belonging to the field of semiconductor packaging and 3D integrated circuit interconnect technology. The seed layer is a four-layer composite seed layer structure sequentially prepared on the wall of the deep via in a glass substrate and the substrate surface, consisting of a PVD-Ti adhesion layer, a chemically plated Ni transition buffer layer, a chemically plated Cu conformal conductive layer, and a PVD surface Cu reinforcing layer. This invention solves problems such as shadowing effect, weak interface bonding, high residual stress, and seed layer disconnection in high aspect ratio TGV deep vias by designing a composite seed layer, achieving void-free metallization of glass vias with an aspect ratio ≥15:1, improving the structural stability and conductivity of the seed layer, and adapting it to the 3D high-density interconnect manufacturing of next-generation glass interposers. Simultaneously, by controlling key PVD parameters, the PVD sputtering effect is significantly improved, allowing the sputtered portion to penetrate deeper into the hole structure, thereby effectively improving the film coverage uniformity and adhesion performance.

The present application relates to a kind of nanoparticle enhanced low temperature interconnection, high temperature service composite spot and its preparation method, belong to advanced electronic packaging material and interconnection field, specifically, it is related to a kind of based on co-deposition electroplating process, face high-density packaging nano-enhanced low temperature interconnection composite micro-bump and its preparation method. Using nanoparticle induced full liquid phase metallurgical reaction, low melting point phase is quickly consumed and converted into high melting point phase in shorter interconnection time. Even if higher temperature is used in interconnection process to ensure full liquid phase fusion, the composite spot after reaction can obtain thermal stability significantly higher than initial melting point, and completely eliminates the risk of remelting in service environment.

The application relates to the technical field of printed circuit board and electronic device board-level interconnection, and particularly provides a board-level interconnection structure resistant to thermal fatigue and a preparation method thereof. The board-level interconnection structure comprises a circuit board, at least one solder pad arranged on the circuit board, a device pin connected to the solder pad through a solder joint, and a device body connected to the device pin, the solder pad comprises a first area for soldering with the device pin and a second area located at the periphery of the first area, the upper surface of the first area is a plane, and the second area is a porous structure. The preparation method is as follows: a metal layer is formed at a preset position of the circuit board, and is patterned into a solder pad, then a hole cavity is formed in the second area of the solder pad, and after surface treatment, the device pin is soldered to the first area. In the application, the second area of the porous structure is located at the periphery of the first area, the generation of thermal stress can be reduced through heat dissipation, and the influence of thermal stress can be reduced through deformation buffering, so that the thermal fatigue resistance of the board-level interconnection structure is improved.