16 results about "Interconnect technology" patented technology

Configurations are disclosed for multi-wavelength optical devices and systems. In particular, multi-wavelength optical devices that include separate chips optically connected via phonic wire bonds. The disclosed configurations can utilize photonic wire bond interconnects and photonic wire bond interconnection techniques, which may facilitate low-cost implementation of wavelength division multiplexed optical systems.

The embodiments of the present disclosure provide a board and a server, which relates to the technical field of processor board card interconnection. By arranging the first internal connectors in the second internal connector configuration area and the second internal connectors in the first internal connector configuration area; the first processor is electrically connected to the first internal connectors through the first circuit, and the second processor is electrically connected to the second internal connectors through the second circuit, and the first circuit and the second circuit are arranged in an intersecting way. Based on the wiring design of the board of the embodiments of the present disclosure for multi-board interconnection, the complexity of the cable topology structure in the board group may be effectively simplified, thereby improving the maintenance efficiency of multi-card interconnection, and reducing the construction difficulty and maintenance cost.

This invention discloses a solderless bonding method for interconnecting flexible micro-LEDs with flexible circuits, belonging to the field of flexible Micro-LED display interconnect technology. The method includes fabricating three layers of metal bumps on chip electrodes, forming a composition-matched receiving layer on a flexible substrate, aligning and bonding them after atomic-level cleaning, and achieving solid-state diffusion bonding under low temperature and low pressure to form a stable intermetallic compound interface. This application effectively solves the problems of thermal stress mismatch, interface delamination, and unstable contact resistance under bending caused by solder bonding, improving the reliability and mass production compatibility of high-density flexible Micro-LED devices.

The application relates to the technical field of optical fiber interconnection, and provides a chip supporting efficient interconnection of multiple heterogeneous hollow core optical fibers and a design method. The chip comprises a first grating, a second grating and a connecting waveguide; the first grating is used for coupling with a first hollow core optical fiber, the second grating is used for coupling with a second hollow core optical fiber; and the connecting waveguide is used for connecting the first grating and the second grating. The application provides a technical scheme for realizing the coupling of corresponding hollow core optical fibers through corresponding gratings, and realizing the interconnection of the hollow core optical fibers through the connection between the gratings and the connecting waveguide. Since the grating and the connecting waveguide are both designed based on a silicon-based chip, the preparation difficulty is low, and batch production is possible.

Exemplary embodiments are disclosed of EMI absorbers that are operable for suppressing and / or absorbing EMI noise at relatively high frequencies for high-speed cables, e. g., cables for interconnect from chip to board, integrated circuit (IC) package to board, input / output (I / O) panel to board, board to board, module to board, subsystem to board, supporting high-speed interconnect technology standards, such as Peripheral Component Interconnect Express (PCIe) Gen 5 / 6 / 7, etc. and Computer Express Link (CXL) 3.1, etc. In exemplary embodiments, the EMI absorber comprises a moldable thermoplastic EMI absorber configured to be operable for suppressing and / or absorbing EMI noise from a cable or another component including frequencies from 5 gigahertz to 70 gigahertz when the EMI absorber is positioned on a portion of the cable or another component, e. g., when the EMI absorber entirely and / or continuously surrounds (e. g., is disposed 360 degrees around, etc.) the portion of the cable or another component.

A semiconductor device assembly including a first module having one or more memory arrays, each of the one or more memory arrays being connected to a plurality of landing pads of the first module; and a second module having complementary metal-oxide-semiconductor devices, the second module including a plurality of socket shallow trench isolation (STI) regions disposed in a substrate of the second module, a plurality of metal routing layers connected to corresponding CMOS devices, a plurality of a first type of via contacts each being connected to a corresponding one of the plurality of metal routing layers, and a plurality of a second type of via contacts each being connected to a corresponding one of the plurality of landing pads of the first module, wherein the plurality of the first type of via contacts and the plurality of the second via contacts pass through the plurality of socket STI regions.

This disclosure provides a shared memory interconnect device, arbitration method, and arbitration circuit, relating to the field of integrated circuit interconnect technology. The implementation scheme is as follows: a hierarchical interconnect network includes an outer routing network and an inner switching network. The outer routing network includes a multi-level switching network composed of multiple butterfly switching units, used to route data stream packets from input ports to multiple subgroups of the inner switching network. The inner switching network includes multiple crossbar switching modules for performing local non-blocking switching. An arbitration module maintains the weights of each input port and determines the arbitration result based on the weights between conflicting ports. When arbitration fails, the weight of the corresponding port is incremented by a preset increment. When arbitration succeeds, the weight of the corresponding port is restored to its initial value. The arbitration result of each port is determined by cascading the arbitration status between conflicting ports, which can significantly reduce hardware area overhead while ensuring local bandwidth and low latency.

The invention provides a contact terminal structure with a self-locking function, and belongs to the technical field of thermal battery electrical interconnection, and the contact terminal structure specifically comprises a jack terminal and a pin terminal, the pin terminal is used for being inserted into the inner wall of the jack terminal, the side wall of the jack terminal is provided with a locking plate which extends inwards in an inclined manner, and the locking plate is provided with a self-locking function. The part, inserted into the jack terminal, of the pin terminal jack terminal comprises a conical head and a main body rod, the conical head is the end, facing the jack terminal, of the pin terminal, the end, facing the jack terminal, of the conical head is a small-diameter end, an annular groove is formed in the periphery of the end, close to the conical head, of the main body rod, and the inner wall, away from the conical head, of the annular groove is an annular conical surface. The small-diameter end of the annular conical surface is close to the conical head; when the pin terminal is inserted into the jack terminal, the locking plate abuts against the annular conical surface, and the innermost side of the locking plate abuts against the wall surface, close to the conical head, of the annular groove. Through the processing scheme of the invention, the connection reliability of the contact terminal is improved.

A seed layer for deep vias in glass and its preparation method are disclosed, belonging to the field of semiconductor packaging and 3D integrated circuit interconnect technology. The seed layer is a four-layer composite seed layer structure sequentially prepared on the wall of the deep via in a glass substrate and the substrate surface, consisting of a PVD-Ti adhesion layer, a chemically plated Ni transition buffer layer, a chemically plated Cu conformal conductive layer, and a PVD surface Cu reinforcing layer. This invention solves problems such as shadowing effect, weak interface bonding, high residual stress, and seed layer disconnection in high aspect ratio TGV deep vias by designing a composite seed layer, achieving void-free metallization of glass vias with an aspect ratio ≥15:1, improving the structural stability and conductivity of the seed layer, and adapting it to the 3D high-density interconnect manufacturing of next-generation glass interposers. Simultaneously, by controlling key PVD parameters, the PVD sputtering effect is significantly improved, allowing the sputtered portion to penetrate deeper into the hole structure, thereby effectively improving the film coverage uniformity and adhesion performance.

The invention relates to the technical field of equipment interconnection, in particular to a display method and device for fusing multiple desktops, and the method comprises the steps: obtaining equipment information of display equipment corresponding to at least two to-be-fused desktops; controlling the display equipment to enter a full desktop fusion mode so as to identify an adaptation strategy, a display mode and an equipment permission of the display equipment based on the equipment information; and on the basis of the adaptation strategy, the display mode and the equipment authority, constructing a full-fusion desktop suitable for the display equipment, and displaying by using the display equipment until a certain exit condition of the full-desktop fusion mode is met. Therefore, the problems that in related technologies, due to the fact that one-way projection is limited in technical architecture, a mobile phone and a vehicle-mounted terminal are completely isolated, fusion display cannot be conducted, operation is tedious, distraction is prone to happening in the driving process, and then driving risks are increased are solved; the self-developed interconnection system is poor in hardware compatibility and difficult in cross-platform adaptation, so that functions and scenes are limited, and multiple requirements of users are difficult to meet.

The invention provides an I / O bonding packaging structure of a flexible electronic chip and a manufacturing method thereof, the I / O bonding packaging structure of the flexible electronic chip comprises a circuit substrate, the upper surface of the circuit substrate is provided with a plurality of bonding pads; the chip is arranged above the circuit substrate, and a plurality of I / O contacts are arranged on the lower surface of the chip; and the plurality of conductive adhesive points are respectively arranged between the corresponding bonding pads and the I / O contacts and are electrically connected with the chip and the circuit substrate. A plurality of conductive adhesive points are arranged between the bonding pad of the circuit substrate and the I / O contact on the lower surface of the chip by using an automatic adhesive dispensing technology, and one-time surface-mount bonding is realized by combining high-precision alignment, so that the packaging efficiency is remarkably improved, high-density interconnection, a low-temperature process, high reliability and low cost are considered, and the product quality is improved. Therefore, the defects of the existing interconnection technology in the aspects of crosstalk, bridging, poor reworking performance, high-temperature damage, coplanarity sensitivity and the like are effectively overcome.

The application provides a chip and a chip package, relates to the technical field of chip interconnection, and can reduce the power consumption and area of a chip interconnection interface. The chip comprises a chip interconnection interface, the chip interconnection interface comprises a buffer, the buffer is a standard unit, one of the output end and the input end of the buffer is connected with a connecting part of a chip active surface, and the other is connected with an internal digital circuit in the chip; and the connecting part of the chip active surface is connected with an external chip.

The invention discloses an efficient multi-physical field modeling method and system for a substrate integrated waveguide filter, and belongs to the field of multi-physical field joint modeling and simulation. Aiming at the problem that the efficiency is insufficient when a traditional modeling method is used for processing a specific structure of the integrated waveguide, the invention innovatively provides a solution strategy customized for multi-physics field coupling of the integrated waveguide. Based on a periodic through hole array of an integrated waveguide, a resonant cavity and a coupling structure characteristic, adaptive subdomain division guided by physical topology is carried out. A finite element separation interconnection technology is introduced, and a global computing domain is divided into a plurality of sub-domains. A Lagrange multiplier specially used for processing electromagnetic, heat and force field data transmission is introduced into a sub-domain interface, and the coupling precision is ensured. According to the method, on the premise of keeping high fidelity, the solving efficiency of a large-scale multi-physical field problem is remarkably improved, and a core technical support is provided for rapid evaluation and optimization design of the performance and reliability of the integrated waveguide filter.

The present application relates to a kind of nanoparticle enhanced low temperature interconnection, high temperature service composite spot and its preparation method, belong to advanced electronic packaging material and interconnection field, specifically, it is related to a kind of based on co-deposition electroplating process, face high-density packaging nano-enhanced low temperature interconnection composite micro-bump and its preparation method. Using nanoparticle induced full liquid phase metallurgical reaction, low melting point phase is quickly consumed and converted into high melting point phase in shorter interconnection time. Even if higher temperature is used in interconnection process to ensure full liquid phase fusion, the composite spot after reaction can obtain thermal stability significantly higher than initial melting point, and completely eliminates the risk of remelting in service environment.

The invention discloses a neuron synchronization and multilayer core particle interconnection technology of a brain-like reasoning chip, and belongs to the field of brain-like calculation. In order to solve the problems that in the prior art, neuron synchronization precision is insufficient, multi-layer core grain interconnection data transmission efficiency is low, and system integration optimization is insufficient, an integrated brain-like reasoning chip architecture is constructed by designing a self-adaptive neuron synchronization module, an efficient multi-layer core grain interconnection module, a reasoning acceleration module and a computing resource scheduling module. The framework realizes vertical integration of core grains based on a 2.5 D packaging technology, guarantees fine synchronization of neurons in large-scale parallel computing through a dynamic synchronization mechanism and accurate time sequence control, improves data transmission efficiency among the core grains, specially adapts to hardware requirements of brain-like reasoning tasks, and remarkably improves accuracy, speed and system throughput of neural network reasoning. The method can be widely applied to the technical fields of artificial intelligence reasoning, integrated circuit design, neuromorphic calculation, brain-computer interfaces and the like.