Aging test verification structure and test method

Abstract

The embodiment of the invention provides an aging test verification structure and a test method, and relates to the technical field of semiconductor design, and the aging test verification structure comprises at least one high-speed plate layer which is provided with a high-speed link and is used for transmitting a high-speed signal; the at least one low-speed plate layer is positioned on one side of the high-speed plate layer, is provided with a low-speed link and is used for transmitting a low-speed signal; the input end is used for acquiring the low-speed signal or the high-speed signal; and the output end is connected with the input end through the high-speed link or connected with the input end through the low-speed link. According to the aging test board, the problem of high measurement cost often occurs when a high-performance aging test board is adopted, so that the effect of saving the test cost is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of semiconductor design, and in particular, to an aging test verification structure and a test method. Background Art

[0002] Aging testing is a method that simulates the various environmental conditions and usage scenarios a product may encounter during actual use. The purpose of this test is to evaluate the performance changes and durability of a product during long-term operation or storage, ensuring that the product can maintain its function and quality throughout its specified service life.

[0003] A burn-in board (BIB) is a printed circuit board (PCB) specifically designed for IC (integrated circuit) burn-in testing. Its purpose is to perform burn-in testing on packaged ICs under specific operating conditions and timeframes to verify IC reliability. Burn-in testing is a process in which semiconductor components are subjected to temperature stress testing to detect failures at an early stage caused by design, material, process, and / or manufacturing defects.

[0004] However, due to the fixed and single structure of current burn-in test boards, they are difficult to adapt to changing test signals. In particular, burn-in test boards are generally not upward compatible, only backward compatible. While a high-performance burn-in test board can measure low-speed test signals, a low-performance burn-in test board cannot meet the requirements of measuring high-speed test signals. Therefore, using a high-performance burn-in test board often leads to high measurement costs. Summary of the Invention

[0005] The embodiments of the present application provide an aging test verification structure and a testing method, which at least solve the problem of high measurement costs often occurring when using high-performance aging test boards in related technologies.

[0006] According to one embodiment of the present application, an aging test verification structure is provided, including: at least one high-speed board layer, provided with a high-speed link for transmitting high-speed signals; at least one low-speed board layer, located on one side of the high-speed board layer, provided with a low-speed link for transmitting low-speed signals; an input end, used to obtain the low-speed signal or the high-speed signal; an output end, connected to the input end through the high-speed link, or connected to the input end through the low-speed link.

[0007] According to another embodiment of the present application, a testing method based on an aging test verification structure is provided, and the testing method is applied to the aging test verification structure as described in any one of the above items, including: obtaining a test signal based on an input end; when the test signal is a high-speed signal, transmitting the test signal based on a high-speed link of a high-speed board layer; when the test signal is a low-speed signal, transmitting the test signal based on a low-speed link of a low-speed board layer; and sending the test signal to a detection device based on the output end, so that the detection device detects the aging test verification structure based on the test signal.

[0008] According to one embodiment of the present application, when the test signal includes a high-speed signal and a low-speed signal, an appropriate board layer (high-speed or low-speed) can be selected. That is, when the test signal is a high-speed signal, the high-speed link of the high-speed board layer is used to transmit the test signal. When the test signal is a low-speed signal, the low-speed link of the low-speed board layer is used to transmit the test signal. Therefore, different types of signals can be tested, thereby effectively solving the problem of high measurement costs often encountered by using high-performance aging test boards in related technologies, thereby achieving the effect of saving testing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a schematic diagram of the aging test verification structure according to an embodiment of the present application. Figure 1 ;

[0010] Figure 2 This is a schematic diagram of the aging test verification structure according to an embodiment of the present application. Figure 2 ;

[0011] Figure 3 This is a schematic diagram of the aging test verification structure according to an embodiment of the present application. Figure 3 ;

[0012] Figure 4 This is a schematic diagram of the aging test verification structure according to an embodiment of the present application. Figure 4 ;

[0013] Figure 5 1 is a schematic structural diagram of an aging test verification structure with a resistor installed according to an embodiment of the present application;

[0014] Figure 6 is a flow chart of a testing method based on an aging test verification structure according to an embodiment of the present application;

[0015] Figure 7 This is a connection diagram of a structure for verifying an aging test using a vector network analyzer (VNA) according to an embodiment of the present application;

[0016] Figure 8This is a connection diagram of a device under test (DUT) test aging test verification structure according to an embodiment of the present application;

[0017] Figure 9 1 is a connection diagram of a resistor test aging test verification structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0018] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0019] It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0020] A burn-in board (BI B board) is a test board specifically designed to test and verify the performance of electronic components during the production process. It is primarily used to verify the stability and reliability of electronic components or entire systems during production. Burn-in testing is an accelerated aging test that simulates potential issues that may arise from prolonged use by operating the device under conditions such as high temperature, high voltage, and high frequency.

[0021] Among them, the main functions of BI B board are as follows:

[0022] Detecting initial failures of electronic components: By performing burn-in testing during the production process, components with potential failures can be discovered and eliminated, thereby improving product reliability.

[0023] Evaluate product life: Through accelerated aging testing, the service life of the product can be predicted, providing a basis for product design and improvement.

[0024] Verify product stability: Burn-in testing can detect the stability of the product during long-term operation to ensure that the product will not malfunction in actual use.

[0025] Improve production efficiency: Burn-in testing can detect and solve problems in the production process in advance, reduce rework and repair costs, and improve production efficiency.

[0026] High-speed ADDA interfaces are found in various high-performance optical modules, RF transceivers, baseband chips, and other applications. These interfaces serve as a bridge between analog and digital technologies. As the overall performance of various chips continues to improve, ADDA sampling rates are also increasing, and with them, the SI (signal integrity) requirements for high-speed signals on the BI B-board. Currently, some chips support ADDA input signal bandwidths exceeding 20 GHz, for example, in optical communications and fixed networks. This poses significant challenges for power-on dynamic aging testing based on BI B-boards.

[0027] In an embodiment of the present application, an aging test verification structure is provided. Figure 1 This is a schematic diagram of the aging test verification structure according to an embodiment of the present application. Figure 1 ,like Figure 1 As shown, the aging test verification structure includes:

[0028] At least one high-speed plate layer is provided with a high-speed link for transmitting high-speed signals;

[0029] At least one low-speed plate layer is located on one side of the high-speed plate layer and is provided with a low-speed link for transmitting low-speed signals;

[0030] Input terminal, used to obtain low-speed signals or high-speed signals;

[0031] The output end is connected to the input end through a high-speed link, or is connected to the input end through a low-speed link.

[0032] Figure 2 This is a schematic diagram of the aging test verification structure according to an embodiment of the present application. Figure 2 In an exemplary embodiment, Figure 2As shown, in the hybrid structure obtained by combining the above-mentioned high-speed plate layer and low-speed plate layer, a TOP layer and a BOTTOM layer are included. Among them, the high-speed plate layer is located in the TOP layer or adjacent to the TOP layer (for example, the 2nd layer, the 3rd layer), and the low-speed plate layer is located in the BOTTOM layer or adjacent to the BOTTOM layer (for example, the 4th layer, the 5th layer, the 6th layer, the 7th layer). Alternatively, the high-speed plate layer is located in the BOTTOM layer or adjacent to the BOTTOM layer (for example, the 4th layer, the 5th layer, the 6th layer, the 7th layer), and the low-speed plate layer is located in the TOP layer or adjacent to the TOP layer (for example, the 2nd layer, the 3rd layer). The input end and the output end are located in the TOP layer or the BOTTOM layer, respectively forming a path with the high-speed link of the high-speed plate layer for transmitting high-speed signals, or respectively forming a path with the low-speed link of the low-speed plate layer for transmitting low-speed signals. For example, the high-speed signal in the embodiment of the present application can be a signal with a clock frequency in the range of megahertz to gigahertz units, and the low-speed signal can be a signal with a clock frequency in the range of hundreds of hertz or kilohertz units.

[0033] Among them, the aging test verification structure can be obtained by combining a layer of high-speed sheet material layer and a layer of low-speed sheet material layer, in which case the high-speed sheet material layer is the TOP layer and the low-speed sheet material layer is the BOTTOM layer, or the aging test verification structure can be obtained by combining a layer of high-speed sheet material layer and multiple low-speed sheet material layers, in which case the high-speed sheet material layer is the TOP layer and the outermost layer of the low-speed sheet material layer away from the high-speed sheet material layer is the BOTTOM layer. Or, the aging test verification structure can be obtained by combining multiple high-speed sheet material layers and a layer of low-speed sheet material layer, in which case the outermost layer of the high-speed sheet material layer away from the low-speed sheet material layer is the TOP layer and the low-speed sheet material layer is the BOTTOM layer. Or, the aging test verification structure can be obtained by combining multiple high-speed sheet material layers and multiple low-speed sheet material layers, in which case the outermost layer of the high-speed sheet material layer away from the low-speed sheet material layer is the TOP layer and the outermost layer of the low-speed sheet material layer away from the high-speed sheet material layer is the BOTTOM layer.

[0034] Alternatively, in the case where the aging test verification structure is a combination of a high-speed sheet material layer and a low-speed sheet material layer, the low-speed sheet material layer is the TOP layer and the high-speed sheet material layer is the BOTTOM layer. Alternatively, the aging test verification structure can be a combination of a low-speed sheet material layer and multiple high-speed sheet material layers, in which case the low-speed sheet material layer is the TOP layer and the outermost layer of the high-speed sheet material layer away from the low-speed sheet material layer is the BOTTOM layer. Alternatively, the aging test verification structure can be a combination of multiple low-speed sheet material layers and a high-speed sheet material layer, in which case the outermost layer of the low-speed sheet material layer away from the high-speed sheet material layer is the TOP layer and the high-speed sheet material layer is the BOTTOM layer. Alternatively, the aging test verification structure can be a combination of multiple low-speed sheet material layers and multiple high-speed sheet material layers, in which case the outermost layer of the low-speed sheet material layer away from the high-speed sheet material layer is the TOP layer and the outermost layer of the high-speed sheet material layer away from the low-speed sheet material layer is the BOTTOM layer.

[0035] It should be noted that the positions of the TOP layer and the BOTTOM layer in the embodiment of the present application can be interchanged and are not limited to the description in the embodiment of the present application.

[0036] In an exemplary embodiment, a soldermask layer is provided on the side of the high-speed plate layer of the TOP layer facing away from the low-speed plate layer, and a soldermask layer is provided on the side of the low-speed plate layer of the BOTTOM layer facing away from the high-speed plate layer.

[0037] In an exemplary embodiment, a soldermask layer is used to protect the high-speed material layer (TOP) and the low-speed material layer (BOTTOM). To facilitate connection of the input and output terminals to external devices, the soldermask layer is provided with holes at the input and output terminals, thereby facilitating connection of the input / output terminals of the external device to the input and output terminals through these holes.

[0038] The high-speed electrical performance of a board is directly related to two performance indicators: the dielectric constant (Dk) and the dissipation factor (Df). Dk is a physical parameter that characterizes the dielectric or polarization properties of a dielectric material. Its value is equal to the ratio of the capacitance of an equivalent capacitor made of the material to be tested to that of a finished product of the same size made of a vacuum medium. This value is also a representation of the material's ability to store electricity. A large Dk means that more of the transmission energy in the signal line will be stored in the board, resulting in poor SI performance of the high-speed signal and a slowdown in the propagation rate. Therefore, the lower the Dk, the better the signal transmission quality. Df characterizes the ratio of the energy that has been lost to the insulating board in the signal line to the energy still remaining in the signal line. It is also called the loss factor, dielectric loss, or loss tangent. Df also mainly affects the SI performance of high-speed signals. The smaller the Df, the smaller the loss of the high-speed signal itself. The Dk and Df indicators of the board are determined by the glass fiber type, resin filling degree, etc. Different glass fiber types and resin filling combinations correspond to different Laminate (also called "core") and Prepreg (also called "pp") models.

[0039] Currently, burn-in BI B boards generally use conventional high-Tg low-speed (LS) laminates, including but not limited to high-Tg FR4 or equivalent. Typical Dk values ​​are approximately 4.4 @ 1 GHz, and Df values ​​are approximately 0.015 @ 1 GHz. High-speed (HS) laminates, including but not limited to Megtron6 ​​or equivalent, have typical Dk values ​​of approximately 3.7 @ 1 GHz, and Df values ​​of approximately 0.002 @ 1 GHz. High-speed HS laminates exhibit superior Dk / Df performance compared to low-speed LS laminates. As the frequency of high-speed signals, such as ADDA, increases, signal insertion loss and return loss also increase, potentially causing signal distortion and adversely affecting HTOL test results. When verifying the reliability of the outer ring of a high-speed ADDA IP, LS laminates fail to meet the test requirements, requiring the use of high-speed laminates. However, high-speed HS laminates are significantly more expensive than low-speed LS laminates. Therefore, using high-speed HS laminates for mass testing of low-speed ADDA signals is costly.

[0040] However, in the embodiment of the present application, the above-mentioned aging test verification structure is used. When the test signal includes a high-speed signal and a low-speed signal, the appropriate board layer (high speed or low speed) can be selected. That is, when the test signal is a high-speed signal, the high-speed link of the high-speed board layer is used to transmit the test signal. When the test signal is a low-speed signal, the low-speed link of the low-speed board layer is used to transmit the test signal. Therefore, different types of signals can be tested, thereby effectively solving the problem of high measurement costs often encountered by using high-performance aging test boards in related technologies, thereby achieving the effect of saving testing costs.

[0041] Figure 3 This is a schematic diagram of the aging test verification structure according to an embodiment of the present application. Figure 3 In one embodiment, Figure 3 As shown, there are two groups of high-speed plate layers, and the low-speed plate layer is arranged between the two groups of high-speed plate layers.

[0042] Figure 4 This is a schematic diagram of the aging test verification structure according to an embodiment of the present application. Figure 4 In an exemplary embodiment, Figure 4 As shown, one group of high-speed sheet material layers is located at the TOP layer or adjacent to the TOP layer (e.g., the 2nd and 3rd layers), another group of high-speed sheet material layers is located at the BOTTOM layer or adjacent to the BOTTOM layer (e.g., the 9th to 11th layers), and the low-speed sheet material layers are located between the two groups of high-speed sheet material layers (e.g., the 4th to 8th layers).

[0043] In the hybrid structure obtained by combining the above-mentioned high-speed sheet material layer and the low-speed sheet material layer, the high-speed sheet material layer includes a PP layer, a core layer, and a copper layer (such as a copper foil layer), and different categories are formed based on the combination of the PP layer, the core layer, and the copper layer. The first type of high-speed sheet material layer includes a copper layer and a PP layer, and the second type of high-speed sheet material layer includes a copper layer and a core layer. The first type of high-speed sheet material layer and the second type of high-speed sheet material layer are arranged alternately. Alternatively, the high-speed sheet material layer can be composed entirely of the first type of high-speed sheet material layer. Alternatively, the high-speed sheet material layer can be composed entirely of the second type of high-speed sheet material layer. Alternatively, the high-speed sheet material layer is obtained by any combination of the first type of high-speed sheet material layer and the second type of high-speed sheet material layer. It should be noted that the number of the first type of high-speed sheet material layer and the second type of high-speed sheet material layer can be set based on actual conditions. Among them, the copper layer is located on the side of the PP layer or the core layer away from the low-speed sheet material layer. The PP layer is located between two adjacent copper layers, and the core layer is located between two adjacent copper layers. The input end and the output end are set at the copper layer located at the TOP layer or at the BOTTOM layer. High-speed ADDA signals are routed on any copper layer to obtain a high-speed link for transmitting high-speed signals.

[0044] Low-speed material layers include PP layers, core layers, and copper layers, with different categories formed based on the combination of these layers. The first type of low-speed material layer consists of one copper layer and one PP layer, while the second type of low-speed material layer consists of one copper layer and one core layer. The first and second types of low-speed material layers are arranged alternately. Alternatively, a low-speed material layer can consist entirely of first type low-speed material layers. Alternatively, a low-speed material layer can consist entirely of second type low-speed material layers. A low-speed material layer can be formed by any combination of first and second type low-speed material layers. It should be noted that the number of first and second type low-speed material layers can be set based on actual conditions. The copper layer is located on the side of the PP or core layer facing away from the high-speed material layer. The PP layer is located between two adjacent copper layers, and the core layer is located between two adjacent copper layers. Low-speed ADDA signals are routed on any copper layer, forming a low-speed link with the input and output ports of the copper layer located on the top or bottom layer to transmit low-speed signals.

[0045] In one embodiment, the overlapping area of ​​the projections of adjacent high-speed links and the projections of the low-speed links is less than or equal to a preset threshold.

[0046] In an exemplary embodiment, Figure 4As shown, the copper layer of the third layer is a high-speed sheet material layer, and the copper layer of the fourth layer is a low-speed sheet material layer. In order to reduce the signal interference caused by the high-speed signal in the high-speed link of the high-speed sheet material layer to the low-speed signal in the low-speed link of the low-speed sheet material layer, the overlapping area of ​​the projection of the adjacent high-speed link (such as the copper layer of the third layer) and the projection of the low-speed link (such as the copper layer of the fourth layer) is less than or equal to the preset threshold, that is, the overlapping area of ​​the projection of the high-speed link and the low-speed link in the TOP layer or the BOTTOM layer is less than or equal to the preset threshold. Among them, the preset threshold can be 0, that is, there is no overlapping part in the projection of the high-speed link and the low-speed link in the TOP layer or the BOTTOM layer. The preset threshold can also be 1%, 5%, 10%, 15%, 20%, etc., that is, there is a partial overlap in the projection of the high-speed link and the low-speed link in the TOP layer or the BOTTOM layer. In particular, when the projections of the high-speed link and the low-speed link on the TOP layer or the BOTTOM layer partially overlap, there is an optimal solution to reduce the signal interference caused by the high-speed signal in the high-speed link of the high-speed board layer to the low-speed signal in the low-speed link of the low-speed board layer, that is, the projections of the high-speed link and the low-speed link on the TOP layer or the BOTTOM layer are perpendicular to each other.

[0047] Similarly, the copper layer of the 9th layer is a high-speed board layer, and the copper layer of the 8th layer is a low-speed board layer. In order to reduce the signal interference caused by the high-speed signal in the high-speed link of the high-speed board layer to the low-speed signal in the low-speed link of the low-speed board layer, the overlapping area of ​​the projection of the adjacent high-speed link (such as the copper layer of the 9th layer) and the projection of the low-speed link (such as the copper layer of the 8th layer) is less than or equal to the preset threshold, that is, the overlapping area of ​​the projection of the high-speed link and the low-speed link in the TOP layer or the BOTTOM layer is less than or equal to the preset threshold. Among them, the preset threshold can be 0, that is, there is no overlapping part in the projection of the high-speed link and the low-speed link in the TOP layer or the BOTTOM layer. The preset threshold can also be 1%, 5%, 10%, 15%, 20%, etc., that is, there is a partial overlap in the projection of the high-speed link and the low-speed link in the TOP layer or the BOTTOM layer. In particular, when the projections of the high-speed link and the low-speed link on the TOP layer or the BOTTOM layer partially overlap, there is an optimal solution to reduce the signal interference caused by the high-speed signal in the high-speed link of the high-speed board layer to the low-speed signal in the low-speed link of the low-speed board layer, that is, the projections of the high-speed link and the low-speed link on the TOP layer or the BOTTOM layer are perpendicular to each other.

[0048] In one embodiment, a grounding unit is provided between adjacent high-speed links and low-speed links.

[0049] In an exemplary embodiment, for example, a ground layer is laid on the entire copper layer of the third layer or a ground copper foil is laid in a localized position, or a ground layer is laid on the entire copper layer of the ninth layer or a localized position, thereby shielding the high-speed signal in the high-speed link of the third copper layer or the ninth copper layer, thereby reducing the interference of the high-speed signal on the low-speed signal in the low-speed link of the low-speed board layer. For example, the projection of the third copper layer or the ninth copper layer on the top layer and the projection of the ground copper foil on the top layer can be made to overlap.

[0050] In one embodiment, the high-speed sheet material layer comprises:

[0051] The first conductor layer is used to set up a high-speed link;

[0052] The first non-conductor layer is arranged between adjacent first conductor layers.

[0053] In an exemplary embodiment, the first conductive layer is the aforementioned copper layer, and the first non-conductive layer is the aforementioned PP layer or core layer. For example, the copper layer is etched to form a high-speed link. One end of the high-speed link is connected to the input terminal via a via, and the other end is connected to the output terminal via a via, to form a pathway, thereby facilitating the transmission of high-speed signals.

[0054] In one embodiment, the low-speed sheet material layer comprises:

[0055] The second conductor layer is used to set up a low-speed link;

[0056] The second non-conductive layer is arranged between adjacent second conductive layers.

[0057] In an exemplary embodiment, the second conductive layer is the aforementioned copper layer, and the second non-conductive layer is the aforementioned PP layer or core layer. For example, the copper layer is etched to form a low-speed link. One end of the low-speed link is connected to the input end through a via, and the other end is connected to the output end through a via, to form a pathway, thereby facilitating the transmission of low-speed signals.

[0058] In one embodiment, the input includes:

[0059] Input terminal solder joint, used to obtain input signal;

[0060] Outputs include:

[0061] Output solder joint, used to output input signals.

[0062] In an exemplary embodiment, input and output solder joints are provided on a copper layer located at the top or bottom layer, so that the input solder joint is connected to one end of a high-speed link through a via or the like, and the output solder joint is connected to the other end of the high-speed link through a via or the like, thereby forming a path to facilitate the transmission of high-speed signals. Alternatively, the input solder joint is connected to one end of a low-speed link through a via or the like, and the output solder joint is connected to the other end of the low-speed link through a via or the like, thereby forming a path to facilitate the transmission of low-speed signals.

[0063] In one embodiment, the input terminal solder joint includes:

[0064] The positive polarity solder joint of the input terminal is used to obtain the differential input signal;

[0065] The negative polarity solder joint of the input terminal is used to obtain the differential input signal;

[0066] The output solder joints include:

[0067] The positive polarity solder joint of the output end is connected to the positive polarity solder joint of the input end based on the high-speed link or the low-speed link to output the input signal;

[0068] The negative polarity solder joint at the output end is connected to the negative polarity solder joint at the input end based on a high-speed link or a low-speed link to output the input signal.

[0069] In an exemplary embodiment, based on the properties of the test equipment, the input solder joints can be divided into positive-polarity input solder joints and negative-polarity input solder joints, and the output solder joints can be divided into positive-polarity output solder joints and negative-polarity output solder joints. The positive-polarity input solder joint has one end connected to the test equipment and the other end connected to the input of the high-speed or low-speed link. The output of the high-speed or low-speed link is connected to the positive-polarity output solder joint. The negative-polarity input solder joint has one end connected to the test equipment and the other end connected to the input of the high-speed or low-speed link. The output of the high-speed or low-speed link is connected to the negative-polarity output solder joint. Therefore, the differential input signal emitted from the test equipment can be returned to the test equipment via the positive-polarity input solder joint, the high-speed or low-speed link, and the positive-polarity output solder joint. Simultaneously, the differential input signal can be returned to the test equipment via the negative-polarity input solder joint, the high-speed or low-speed link, and the negative-polarity output solder joint. Thus, the test equipment can measure the electrical performance of the aging test verification structure based on the differential input signal returned by the positive polarity solder joint of the output end and the negative polarity solder joint of the output end.

[0070] In one embodiment, multiple groups of input terminals and output terminals are provided to obtain different detection areas, so as to detect different positions of the aging test verification structure.

[0071] In an exemplary embodiment, different positions of the aging test verification structure are set as different detection areas, and each detection area is provided with an input end and an output end, so that different positions of the aging test verification structure can be detected simultaneously, which can improve the test efficiency.

[0072] In one embodiment, the different detection areas are evenly distributed within the burn-in test verification structure.

[0073] In one exemplary embodiment, evenly distributing the test areas within the burn-in test verification structure facilitates rational location planning and efficient utilization of the burn-in test verification structure. Furthermore, adjacent locations can be used to test similar characteristics, facilitating comparison of test results. This facilitates rapid identification of issues when abnormal test results are detected.

[0074] In one embodiment, at least one resistor is located at different positions of the burn-in test verification structure to measure deformation of the different positions of the burn-in test verification structure based on a simulated voltage across the resistor.

[0075] Figure 5 This is a schematic diagram of a burn-in test verification structure with resistors installed according to an embodiment of the present application. In an exemplary embodiment, resistors are installed at different positions of the burn-in test verification structure to use the resistors as sensors for measuring the physical properties of the positions of the burn-in test verification structure. For example, Figure 5 As shown, resistor 1 is placed at the upper left corner of the aging test verification structure, resistor 2 is placed at the upper right corner, resistor 3 is placed at the lower left corner, and resistor 4 is placed at the lower right corner. The analog voltages of resistor 1, resistor 2, resistor 3, and resistor 4 are collected respectively. Based on the analog voltages of resistor 1, resistor 2, resistor 3, and resistor 4, whether deformation occurs at the upper left corner, upper right corner, lower left corner, and lower right corner of the aging test verification structure is measured. For example, the deformation can be problems such as warping and fracture. Of course, the number and position of the above resistors are only exemplary, and the number and position of the resistors can be determined based on actual conditions.

[0076] In an embodiment of the present application, a test method based on an aging test verification structure is further provided. The test method is applied to the aging test verification structure described above. Figure 6 Flowchart of the test method based on the aging test verification structure according to the embodiment of the present application. Figure 6 As shown, the process includes the following steps:

[0077] Step S601, obtaining a test signal based on an input terminal;

[0078] Step S602: When the test signal is a high-speed signal, the test signal is transmitted based on the high-speed link of the high-speed board layer;

[0079] Step S603: When the test signal is a low-speed signal, the test signal is transmitted based on the low-speed link of the low-speed plate layer;

[0080] Step S604: sending the test signal to the detection device based on the output terminal, so that the detection device detects the aging test verification structure based on the test signal.

[0081] In an exemplary embodiment, a test signal is obtained from a detection device based on an input end, and the test signal is analyzed. If the test signal is a high-speed signal, the test signal is transmitted from a high-speed link of a high-speed plate layer so that the test signal is returned from an output end to the detection device, so that the detection device measures the electrical performance of the aging test verification structure based on the returned test signal. If the test signal is a low-speed signal, the test signal is transmitted from a low-speed link of a low-speed plate layer so that the test signal is returned from an output end to the detection device, so that the detection device measures the electrical performance of the aging test verification structure based on the returned test signal.

[0082] Through steps S601 to S604, if the burn-in test verification structure includes an input terminal, a high-speed link located on a high-speed material layer, a low-speed link located on a low-speed material layer, and an output terminal, and the input terminal, high-speed link, and output terminal form a path for transmitting high-speed signals, and the input terminal, low-speed link, and output terminal form a path for transmitting low-speed signals, then test signals can be transmitted separately based on their type, thereby improving test efficiency and reducing testing costs for the burn-in test verification structure.

[0083] In one embodiment, the detection device is a vector network analyzer (VNA) or a device under test (DUT).

[0084] Figure 7 FIG. 1 is a connection diagram of a structure for verifying an aging test using a vector network analyzer (VNA) according to an embodiment of the present application. In an exemplary embodiment, as shown in FIG. Figure 7 As shown, the probes extending from the transmit port TX of the vector network analyzer (VNA) include a positive transmit probe and a negative transmit probe. The positive transmit probe is connected to the positive solder joint at the input of the aging test verification structure, and the negative transmit probe is connected to the negative solder joint at the input of the aging test verification structure. The probes extending from the receive port RX of the vector network analyzer (VNA) include a positive receive probe and a negative receive probe. The positive receive probe is connected to the positive solder joint at the output of the aging test verification structure, and the negative receive probe is connected to the negative solder joint at the output of the aging test verification structure.

[0085] Therefore, the differential input signal emitted from the transmitting port of the vector network analyzer VNA passes through the path of the positive polarity solder joint at the input end, the high-speed link or the low-speed link, and the positive polarity solder joint at the output end, and at the same time returns to the vector network analyzer VNA through the path of the negative polarity solder joint at the input end, the high-speed link or the low-speed link, and the negative polarity solder joint at the output end, so that the vector network analyzer VNA tests the electrical performance of the aging test verification structure based on the differential input signal returned from the positive polarity solder joint at the output end and the negative polarity solder joint at the output end.

[0086] Figure 8 FIG. 1 is a connection diagram of a device under test DUT test aging test verification structure according to an embodiment of the present application. In an exemplary embodiment, as shown in FIG. Figure 8 As shown, the input port of the device under test (DUT) is connected to the input terminal, and the output port is connected to the output terminal. The device under test (DUT) sends a DAC (digital analog signal) from the input port. The DAC (digital analog signal) returns to the device under test (DUT) via the input terminal, a high-speed link or a low-speed link, and the output terminal to obtain an ADC (analog digital signal). The electrical performance of the aging test verification structure is tested based on the ADC (analog digital signal).

[0087] In one embodiment, the method further comprises:

[0088] Sending an analog voltage across at least one resistor provided on the aging test verification structure to a host computer, so that the host computer compares the analog voltage with a preset voltage threshold;

[0089] When the simulated voltage exceeds a preset voltage threshold, it is determined that the aging test verification structure has been deformed.

[0090] Figure 9 is a connection diagram of a resistor test aging test verification structure according to an embodiment of the present application. In an exemplary embodiment, as Figure 5 and Figure 9 As shown, resistors are set at different positions of the aging test verification structure to use the resistors as sensors for measuring the physical properties of the positions of the aging test verification structure. Figure 5As shown, resistor 1 is placed at the upper left corner of the aging test verification structure, resistor 2 is placed at the upper right corner, resistor 3 is placed at the lower left corner, and resistor 4 is placed at the lower right corner. The analog voltages of resistor 1, resistor 2, resistor 3, and resistor 4 are collected respectively to measure whether deformation occurs at the upper left corner, upper right corner, lower left corner, and lower right corner of the aging test verification structure based on the analog voltages of resistor 1, resistor 2, resistor 3, and resistor 4. For example, the deformation can be problems such as warping and fracture. Each resistor is powered by a power supply to generate an analog voltage value. It should be noted that resistor 1, resistor 2, resistor 3, and resistor 4 can be powered by the same power supply, or they can be powered by separate power supplies.

[0091] In one embodiment, the method further includes: amplifying the analog voltage to a preset multiple based on a differential amplifier.

[0092] In an exemplary embodiment, Figure 9 As shown, the analog potential outputted from each resistor is amplified by a differential amplifier to obtain an analog voltage, so that the host computer can analyze the amplified voltage. The preset multiple can be determined based on the host computer. Specifically, in order to adapt to different host computers, a related circuit can be designed to realize the amplification of the analog voltage. Moreover, based on the differential amplifier, there are advantages such as being able to suppress common-mode noise, high precision, strong stability, strong anti-interference ability, balanced load, easy to implement, reducing parasitic effects, and high flexibility. Therefore, the stability, precision, and anti-interference ability of the analog voltage across the measuring resistor are improved.

[0093] In one embodiment, the method further includes: converting the analog voltage amplified to a preset multiple into a digital voltage based on an analog-to-digital converter, so that the host computer compares the digital voltage with a preset voltage threshold.

[0094] In an exemplary embodiment, Figure 9 As shown, the analog voltage amplified by the differential amplifier can be converted into a digital voltage via an analog-to-digital converter. Specifically, the digital voltage can be transmitted, calculated, and processed in the form of a digital code, so that the host computer can infer the initial voltage value collected from resistor 1, resistor 2, resistor 3, and resistor 4 based on the digital code, so that the host computer can compare the initial voltage value with the preset voltage threshold. When the initial voltage value exceeds the preset voltage threshold, it is determined that the aging test verification structure has been deformed. Of course, the analog-to-digital converter can convert the amplified analog voltages of multiple resistors at the same time, and then send the digital voltage to the host computer through a bus such as SPI / I2C, so that the host computer can process multiple digital voltages in batches.

[0095] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by adding the necessary general hardware platform with the help of software, of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0096] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0097] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included within the scope of protection of the present application.

Claims

1. An aging test verification structure, characterized in that: include: At least one high-speed plate layer is provided with a high-speed link for transmitting high-speed signals; At least one low-speed plate layer, located on one side of the high-speed plate layer, provided with a low-speed link for transmitting low-speed signals; An input terminal, used for obtaining the low-speed signal or the high-speed signal; The output end is connected to the input end through the high-speed link, or is connected to the input end through the low-speed link.

2. The structure according to claim 1, characterized in that The high-speed plate layer is provided in two groups, and the low-speed plate layer is provided between the two groups of the high-speed plate layers.

3. The structure according to claim 1, characterized in that An overlapping area between the projections of the adjacent high-speed links and the projections of the low-speed links is smaller than or equal to a preset threshold.

4. The structure according to claim 1, characterized in that A grounding unit is provided between adjacent high-speed links and low-speed links.

5. The structure according to claim 1, characterized in that The high-speed plate layer includes: A first conductor layer, used for setting the high-speed link; The first non-conductor layer is arranged between adjacent first conductive layers.

6. The structure according to claim 1, characterized in that The low-speed plate layer comprises: A second conductor layer, used for setting the low-speed link; The second non-conductive layer is disposed between adjacent second conductive layers.

7. The structure according to claim 1, characterized in that The input terminal includes: Input terminal solder joint, used to obtain input signal; The output terminal includes: The output terminal solder joint is used to output the input signal.

8. The structure according to claim 7, characterized in that The input terminal solder joint includes: The positive polarity solder joint of the input terminal is used to obtain the differential input signal; The negative polarity solder joint of the input terminal is used to obtain the differential input signal; The output terminal welding point includes: The output end positive polarity solder joint is connected to the input end positive polarity solder joint based on the high-speed link or the low-speed link to output the input signal; The negative-polarity solder joint at the output end is connected to the negative-polarity solder joint at the input end based on the high-speed link or the low-speed link to output the input signal.

9. The structure according to claim 1, characterized in that The input end and the output end are provided in multiple groups to obtain different detection areas, so as to detect different positions of the aging test verification structure.

10. The structure according to claim 9, characterized in that The different detection areas are evenly distributed within the aging test verification structure.

11. The structure according to claim 1, characterized in that Also includes: At least one resistor is located at different positions of the burn-in test verification structure to measure deformation of the different positions of the burn-in test verification structure based on a simulated voltage of the resistor.

12. A test method based on an aging test verification structure, the test method being applied to the aging test verification structure as claimed in any one of claims 1 to 11, characterized in that: include: Acquire a test signal based on an input terminal; In the case where the test signal is a high-speed signal, the test signal is transmitted via a high-speed link based on the high-speed plate layer; When the test signal is a low-speed signal, the test signal is transmitted via a low-speed link based on the low-speed plate layer; The test signal is sent to a detection device based on the output terminal, so that the detection device detects the aging test verification structure based on the test signal.

13. The testing method according to claim 12, characterized in that: The detection device is a vector network analyzer (VNA) or a device under test (DUT).

14. The testing method according to claim 12, wherein: Also includes: Sending an analog voltage across at least one resistor provided on the aging test verification structure to a host computer, so that the host computer compares the analog voltage with a preset voltage threshold; When the simulation voltage exceeds the preset voltage threshold, it is determined that the aging test verification structure is deformed.

15. The testing method according to claim 14, characterized in that: Also includes: The analog voltage is amplified to a preset multiple based on a differential amplifier.

16. The testing method according to claim 14, characterized in that: Also includes: The analog voltage amplified to a preset multiple is converted into a digital voltage based on an analog-to-digital converter, so that the host computer compares the digital voltage with a preset voltage threshold.

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