145results about How to "Avoid etch damage" patented technology

The present invention provides a method for manufacturing a semiconductor device having high characteristic and reliability. The etching damage during dry etching after forming an electrode or a wiring over an insulating film is prevented. The damage is suppressed by forming a conductive layer so that charged particles due to plasma during dry etching are not generated in a semiconductor layer. Accordingly, it is an object of the invention to provide a method not for generating the deterioration of the transistor characteristic especially in a thin film transistor having a minute structure.

Provided are a nitride semiconductor device having an excellent boundary between a nitride semiconductor and a gate insulating film, resulting in improved device characteristics, and a manufacturing method therefor. The nitride semiconductor device includes: an electron transport layer made of a nitride semiconductor; an electron supply layer layered on the electron transport layer, the electron supply layer being made of a nitride semiconductor including Al and having an Al composition different from that of the electron transport layer; a source electrode and a drain electrode formed on the electron supply layer with a gap therebetween; a gate insulating film covering the surface of the electron supply layer between the source electrode and the drain electrode; a passivation film covering a surface of the gate insulating film and having an opening between the source electrode and the drain electrode; and a gate electrode having a main gate body in the opening facing the electron supply layer through the gate insulating film.

A display substrate includes a data pad on a base substrate, a first buffer layer which covers the data pad, a second buffer layer pattern which is disposed on the first buffer layer and separated from the data pad in a plan view, an active layer on the second buffer layer pattern, a gate insulation layer pattern on the active layer, both ends of the active layer exposed by the gate insulation layer pattern, and a gate electrode on the gate insulation layer pattern.

A method for improving performance of a fin field-effect transistor comprises the steps of providing a substrate, wherein discrete fin parts are formed on a surface of the substrate, an isolation layer is also formed on the surface of the substrate and covers surfaces of a part of side walls of the fin parts, and the top of the isolation layer is lower than the tops of the fin parts; forming a gate structure bridging the fin parts on a surface of the isolation layer, wherein the gate structure covers the surfaces of a part of tops and the side walls of the fin parts; forming an amorphous material layer covering the surfaces of a part of tops and the side walls of the fin parts and the surface of the isolation layer; forming an oxide doping layer on a surface of the amorphous material layer; annealing the oxide doping layer so that doping ions are diffused and enter the fin parts, and forming doping regions in the fin parts at two sides of the gate structure; and removing the oxide doping layer. During the process of removing the oxide doping layer, the amorphous material layer has a protection effect on the isolation layer, the etching loss caused by the technology of removing the oxide doping layer on the isolation layer is prevented, so that the thickness of the isolation layer is maintained unchanged, and the electrical property of the formed fin field-effect transistor is further improved.

The invention discloses a 3D computer flash memory device and a manufacturing method thereof, and a buffer layer manufacturing method. The manufacturing method includes the following steps: providinga substrate; forming a stacked structure on the surface of the substrate, wherein the stacked structure includes multilayer oxide layers and multilayer nitride layers, and the oxide layers and the nitride layers are alternately arranged; forming a first channel through hole penetrating the stacked structure and extending into the surface of the substrate, wherein the width of the first channel through hole gradually increases from bottom to top; forming a channel structure on the surface of the substrate exposed by the first channel through hole; forming a function layer on the sidewall of thefirst channel through hole and on the surface of the channel structure; forming a buffer layer on the surface of the function layer, wherein the buffer layer has the minimum thickness at the bottom,and the sidewall thickness gradually increases from bottom to top; and forming a second channel through hole penetrating the bottom of the buffer layer and the bottom of the function layer, and exposing part of the channel structure. According to the technical scheme of the invention, corrosion damage to the function layer can be completely avoided, and the reliability of the device is improved.

A method of manufacturing a semiconductor device, comprising the steps of: forming a gate dielectric layer and a first amorphous channel layer on a substrate; thinning the first amorphous channel layer; etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed; forming a second amorphous channel layer on the first amorphous channel layer and the substrate; annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer; and thinning the polycrystalline channel layer. According to the method of manufacturing semiconductor device of the present invention, the grain size of the polycrystalline thin film is increased by depositing a thick amorphous film and then annealing and thinning it. An additional protective layer is used to avoid etching damage on the sidewalls, effectively reducing the interface state and damage defects of the polycrystalline channel layer, thereby enhancing the reliability of the device.

Both a HEMT and a SBD are formed on a nitride semiconductor substrate. The nitride semiconductor substrate comprises a HEMT gate structure region and an anode electrode region. A first laminated structure is formed at least in the HEMT gate structure region, and includes first to third nitride semiconductor layers. A second laminated structure is formed at least in a part of the anode electrode region, and includes first and second nitride semiconductor layers. The anode electrode contacts the front surface of the second nitride semiconductor layer. At least in a contact region in which the front surface of the second nitride semiconductor layer contacts the anode electrode, the front surface of the second nitride semiconductor layer is finished to be a surface by which the second nitride semiconductor layer forms a Schottky junction with the anode electrode.

A method of producing a reflective mask is carried out by the use of a reflective mask blank which has a substrate, a multilayer reflective film formed on the substrate to reflect exposure light, a protective film formed on the multilayer reflective film, a buffer film formed on the protective film, and an absorber film formed on the buffer film to absorb the exposure light. The protective film is made of a ruthenium compound containing Ru and Nb. The method includes a step of patterning the buffer film by dry etching performed by the use of an etching gas containing oxygen.

Provided is a three-dimensional memory device including a substrate, first and second stacked structures and an etching stop layer. The substrate has a cell region and a periphery region. The first stacked structure is disposed on the cell region and the periphery region, and has a first vertical channel pillar on the cell region that penetrates through the first stacked structure. The second stacked structure is located on the first stacked structure, is disposed on the cell region and the periphery region, and has a second vertical channel pillar on the cell region that penetrates through the second stacked structure. The second vertical channel pillar is electrically connected to the first vertical channel pillar. The etching stop layer is located between the first and second stacked structures, is disposed on the cell region and extends onto the periphery region, and surrounds the lower portion of the second vertical channel pillar.

The invention discloses a formation method of a semiconductor device. The method comprises the following steps: forming a tunneling dielectric layer on a substrate of a flash memory area, a reference unit zone and a logic zone, wherein the tunneling dielectric layer is also disposed on a flash memory grid and a source grid; forming a word line layer on the tunneling dielectric layer; forming a first photoresist layer on the word line layer of the flash memory zone and a part of the word line layer of the reference unit zone; by taking the first photoresist layer as a mask layer, removing the word line layer disposed on the logic zone through etching, and also removing the word line layer exposed on the reference unit zone through etching, wherein the residual word line layer on the reference unit zone is used for forming a reference unit grid; after the reference unit grid is formed, forming a logic grid on the substrate of the logic zone; forming a second photoresist layer on the logic grid and the reference unit grid; and after the second photoresist layer is formed, etching the word line layer of the flash memory zone, and forming a word line on the substrate of the flash memory zone. According to the invention, the morphology of the reference unit grid of a reference unit device is improved, and electrical performance of the formed semiconductor device is improved.

The invention provides a photoetching and etching method for preventing shaped wafer surface from etching damage. The method comprises following steps of forming a floating gate layer and a storage unit control gate layer on a substrate in a storage unit region; forming a gate polysilicon layer on the substrate in a periphery region; depositing advanced patterned film on the substrate; forming a gap filling material layer on the advanced patterned film, thus filling the concave and convex parts of the advanced patterned film; carrying out shape planarization on the advanced patterned film by using a planarization back processing technology; depositing anti-reflection coating film; coating photoresist; forming photoresist patterns; and executing etching processing by using the photoresist patterns, thus etching the floating gate layer and the storage unit control gate layer.

This patent relates to a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include a semiconductor substrate in which a tunnel insulating layer, and a first conductive layer. At least a portion of the semiconductor substrate is removed to form a trench. A first insulating layer may be formed on an internal surface of the trench. A shield layer may be made of a conductive material is formed on the first insulating layer. A second insulating layer may be formed on the shield layer and is configured to gap fill the trench.

The invention relates to a manufacturing method of a semiconductor structure. The method includes the following steps that: a substrate and discrete fins on the substrate are provided, the extending direction of the fins is a first direction, and a direction perpendicular to the first direction is a second direction; an initial isolation layer between the fins is formed on the substrate and includes a first initial isolation layer for achieving the isolation of the fins in the first direction; part of the first initial isolation layer is removed by a certain thickness, so that a first isolation layer is formed, and the top of the first isolation layer is lower than the tops of the fins, and a trench is formed between the fins; a second isolation layer filling the trench is formed; protective sidewalls are formed on the sidewalls of the second isolation layer which are higher than the tops of the fins; and part of a second initial isolation layer and the second isolation layer are removed by a certain thickness. According to the manufacturing method of the semiconductor structure of the invention, the protective sidewalls are formed on the sidewalls of the second isolation layer which are higher than the tops of the fins, and therefore, when part of the second isolation layer is removed by a certain thickness, the protective sidewalls can protect the sidewalls of the second isolation layer, and therefore, the problem of the formation of protrusion defects of the second isolation layer because of insufficient lateral etching can be avoided.

A formation method of a 3D NAND memory comprises the steps of: providing a semiconductor substrate, forming a stacked structure on the semiconductor substrate, wherein the stacked structure comprisesa plurality of alternately stacked sacrificial layers and isolation layers, the stacked structure comprises a first channel hole and a second channel hole, the second channel hole communicates with the first channel hole, the second channel hole has an alignment offset relative to the first channel hole, and a step is formed at the junction of the first channel hole and the second channel hole; etching the step to slow down the gradient of the step; after the step is etched, forming a charge storage layer at the side walls and the bottom portions of the first channel hole and the second channel hole; forming a channel hole sacrificial layer on the charge storage layer; and etching the channel hole sacrificial layer and the charge storage layer at the bottom portion of the first channel hole in order to form an opening. The formation method of the 3D NAND memory can prevent the charge storage layer at the step from being broken by cutting or being damaged so as to avoid failure of the memory.