Integration method of vertical nano-wire transistor

An integration method, nanowire technology, applied in nanotechnology, nanotechnology, nanotechnology for information processing, etc., can solve problems such as limiting the improvement of device performance and difficult to use gate-last process, to improve consistency, avoid Etch damage and performance improvement effect
CN105374752AActive Publication Date: 2016-03-02PEKING UNIV
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
PEKING UNIV
Publication Date
2016-03-02

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Abstract

The invention discloses an integration method of a vertical nano-wire transistor, and belongs to the field of field effect transistor logic devices in CMOS ULSI. According to the method, graphical extension is combined with a sidewall alternative gate to realize integration of the vertical nano-wire transistor. Compared with a present method in which vertical nano wire channels are formed by etching, the sectional area and morphology of the channel of the control device can be accurately controlled, the characteristic consistency of the device is improved, damage caused by etching in the channel formation process is avoided, and the device performance is improved.
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Description

Technical field

[0001] The invention belongs to the technical field of ultra-large-scale integrated circuit manufacturing, and relates to a method combining patterned epitaxy and sidewall replacement gates to achieve vertical nanowire transistor integration. Background technique

[0002] When the semiconductor device enters the 22nm technology generation, the horizontal channel three-dimensional multi-gate device (Multi-gateMOSFET, MuGFET) represented by the fish fin field effect transistor (FinFET), with its outstanding ability to suppress the short channel effect, high integration density , Compatibility with traditional CMOS technology and other advantages, has become the mainstream of semiconductor devices.

[0003] However, when moving toward a smaller size technology node, horizontal channel three-dimensional multi-gate devices are faced with challenges such as difficulty in reducing the spacing of contact holes (limiting the increase in integration density) and gate etching ...

Claims

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