Photoetching and etching method for preventing shaped wafer surface from etching damage

Abstract

The invention provides a photoetching and etching method for preventing shaped wafer surface from etching damage. The method comprises following steps of forming a floating gate layer and a storage unit control gate layer on a substrate in a storage unit region; forming a gate polysilicon layer on the substrate in a periphery region; depositing advanced patterned film on the substrate; forming a gap filling material layer on the advanced patterned film, thus filling the concave and convex parts of the advanced patterned film; carrying out shape planarization on the advanced patterned film by using a planarization back processing technology; depositing anti-reflection coating film; coating photoresist; forming photoresist patterns; and executing etching processing by using the photoresist patterns, thus etching the floating gate layer and the storage unit control gate layer.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, more specifically, the invention relates to a photolithographic etching method for preventing etching damage on the surface of a wafer with topography. Background technique [0002] In the flash memory process, due to the requirements for the formation of the flash memory area and the peripheral area, the polysilicon process of the control gate and the peripheral gate of the memory cell is usually carried out in two steps. [0003] In the case of large design specifications and line widths, traditional photolithography processes such as KrF can use thick photoresist solutions to ensure sufficient photoresist barrier layers. [0004] However, when the line width is lower than a certain specification, an immersion lithography solution is required. The conventional process is: first fill with an advanced patterned film, then fill with an anti-reflective coating (BARC), and then perform a l...

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Problems solved by technology

[0005] However, according to this conventional process as shown in the figure: the process of gate polysilicon treatment and then control gate treatment, due to the height difference in the formed peripheral gate polysilicon area, the thickness of the anti-reflection coating in this area is much thinner than In the memory cell area, it is very prone to etch damage due to insufficient blocking of advanced patterned film in the gate polysilicon area during the etching process

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