105results about How to "Increase window" patented technology

A structure of an interference display cell is provided. The cell comprises a first plate and a second plate, wherein a support is located between the first plate and the second plate. The second plate is a deformable and reflective plate. An incident light from one side of the first plate is modulated and only specific frequency light reflects by the second plate. The frequency of the reflected light is related to the distance between the first plate and the second plate. The support has at least one arm. The arm's stress makes the arm hiking upward or downward. The distance between the first plate and the second plate is also changed. Therefore, the frequency of the reflected light is altered.

An interference display unit with a first electrode, a second electrode and posts located between the two electrodes is provided. The characteristic of the interference display unit is that the second electrode's stress is released through a thermal process. The position of the second electrode is shifted and the distance between the first electrode and the second electrode is therefore defined. A method for fabricating the structure described as follow. A first electrode and a sacrificial layer are sequentially formed on a substrate and at least two openings are formed in the first electrode and the sacrificial layer. A supporter is formed in the opening and the supporter may have at least one arm on the top portion of the supporter. A second electrode is formed on the sacrificial layer and the supporter and a thermal process is performed. Finally, The sacrificial layer is removed.

A method for fabricating an interference display unit is provided. A first plate and a sacrificial layer are formed in order on a substrate and at least two openings are formed in the first plate and the sacrificial layer. A photoresist layer is spin-coated on the sacrificial layer and fills the openings. A photolithographic process patterns the photoresist layer to define a support with an arm. A second plate is formed on the sacrificial layer and posts. The arm's stress is released through a thermal process. The position of the arm is shifted and the distance between the first plate and the second plate is therefore defined. Finally, The sacrificial layer is removed.

The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.

A beverage container having an inner core and an outer shell, relatively rotatable such that a spiral groove in the inner core can be rotationally aligned with cooling flanges on the outside of the outer shell for cleaning, or rotated to close the cooling flanges, forming a cooling tube from the inside of the inner core to a drinking tube at the top of the container, thereby cooling a beverage that is drawn through the cooling flanges by radiating heat into the ambient environment.

The invention discloses a high-strength and corrosion-resistant Al-Mg-Zr aluminum alloy welding stick and a preparation method thereof. The proportion of alloy elements in an Al-Mg-Zr alloy is controlled in an optimized manner, and meanwhile, powder preparation, hot isostatic pressing, extrusion, continuous extrusion and drawing processes are adopted for preparing the welding stick with the fine crystalline grains, uniform structure and the good comprehensive performance. The novel alloy welding stick has the good formability and the low hot cracking tendency in the TIG or MIG welding formingprocess, a welding joint has the high strength and excellent corrosion resistance, the welding stick can be used for welding corrosion-resistant Al-Mg series alloys and high-strength Al-Zr-Mg series alloys, welding requirements of all-aluminum ship and warship bodies and armor protection decks are met, and the application prospects are broad.

Graphene oxide quantum dots (GOQDs) a composite nanomaterial formed by the GOQDs with graphene and/or graphene-like structure(s), and methods for preparing them are provided. The method for preparing GOQDs comprises providing a carbon-based 3D bulk material having a graphite layer structure as an anode, positioning an end face of the material in contact and parallel with the liquid surface of an electrolyte solution, and intermittently or continuously cutting and exfoliating graphite layers at the end face by electrochemical oxidation to obtain GOQDs. The method for preparing the composite nanomaterial comprises adding powder comprising graphite and/or graphite-like layer structure(s) to a solution of GOQDs; under an assistant mechanical action of high shearing force, subjecting the GOQDs adsorbed onto the graphite and/or graphite-like layer structure(s) in the solution to a cycle of exfoliation, re-adsorption, and re-exfoliation, to obtain a composite nanomaterial formed by quasi-zero and/or quasi-two dimensional graphene and/or graphene-like structure(s) and GOQDs.

The invention provides a base editing tool and application thereof. The base editing tool is characterized by comprising GCN4-D10A, a scFv-APOBEC-UGI vector or a scFv-APOBEC-UGI-GB1 vector, and sgRNAat target specific sites, wherein the GCN4-D10A is formed by connecting multi-copied GCN4 to D10A-Cas9; the scFv-APOBEC-UGI vector is formed by connecting cytosine deaminase APOBEC and uracil glycosylase inhibitors UGI to a single-chain antibody scFv; the scFv-APOBEC-UGI-GB1 vector is formed by connecting the cytosine deaminase APOBEC and uracil glycosylase inhibitors UGI and a thermal stability domain GB1 for preventing multimerization to the single-chain antibody scFv. Compared with a commonly used base editing tool, the base editing tool disclosed by the invention has the advantages that the base editing windows are obviously increased, and the application range of base editing in genome is further widened.

The application discloses a surface correction structure and correction method of a semiconductor structure. The surface correction structure comprises a back film and a stress layer adjacent to the back film. The back film is arranged on the surface of the semiconductor structure and is adjacent to the surface of the semiconductor structure. According to the correction structure, a flat surface is provided for the follow-up cover layer and the correction structure is suitable for surface warping with various directivity, so that the yield and reliability of the semiconductor device are improved.

The invention relates to a method for producing Nb-containing high-speed train wheel steel, and belongs to the field of metal materials. The wheel steel comprises the following components in percentage by weight: 0.40 to 0.70 percent of C, 0.70 to 0.80 percent of Mn, 0.30 to 0.60 percent of Si, 0.015 to 0.110 percent of Nb, 0.20 to 0.35 percent of Cr, less than or equal to 0.020 percent of P, less than or equal to 0.015 percent of S and the balance of Fe and inevitable elements. The method comprises the following steps of: smelting, forging to obtain a steel billet, performing normalization and heat preservation at the temperature of between 850 and 900 DEG C for 1 hour, performing air cooling or water spray cooling to room temperature, and ensuring that cooling speed is controlled in therange of 1 to 15 DEG C/s and a room temperature structure is ferrite and pearlite. The high-speed train wheel steel produced by the method has the tensile strength of 740 to 900MPa, the yield strength of 450 to 570MPa, the breaking elongation of 15 to 25 percent and the low temperature (-20 DEG C) impact work (Akv) of 15 to 20J, and a uniform structure with 10 to 25 percent of ferrite can be obtained at room temperature. The Nb-containing high-speed train wheel steel has mechanical properties of high strength and toughness, and overcomes the defect of a low toughness value of the conventionalhigh and medium carbon wheel steel.

The invention discloses a growth method for an epitaxial structure of an LED. The method sequentially comprises the following steps of treating a substrate, growing a low temperature buffer layer GaN,growing a non-doped GaN layer, growing an Si-doped N-type GaN layer, growing a multi-quantum-well layer, growing an AlGaN electronic barrier layer, growing an Mg-doped P-type GaN layer and cooling, wherein growing the multi-quantum-well layer sequentially comprises the following steps of pretreating, growing an Iny1Ga(1-yL)N layer, growing an Iny2Ga(1-y2)N layer, carrying out high-temperature treatment and growing a GaN layer. The method solves the problems that the growth quality of a quantum well is poor and the radiative recombination efficiency of the quantum well is low in an existing epitaxial growth method for the LED, so that the luminous efficiency of the LED is improved, the warping of an epitaxial wafer is reduced, and the yield of products is improved.

The invention discloses an LED epitaxial structure growth method. The method comprises steps: a sapphire substrate is processed; a low-temperature GaN buffer layer grows on the sapphire substrate, thelow-temperature GaN buffer layer is processed, and an irregular island is formed on the low-temperature GaN buffer layer; an undoped GaN layer grows on the low-temperature GaN buffer layer; a Si-doped N-type GaN layer grows on the undoped GaN layer; a multi-quantum well layer grows on the Si-doped N-type GaN layer; an AlGaN electron blocking layer grows on the multi-quantum well layer; a Mg-dopedP-type GaN layer grows on the AlGaN electron blocking layer; and temperature reduction and cooling are carried out. According to the growth method disclosed in the invention, the light emitting efficiency of the LED can be effectively enhanced, warpage of the epitaxial wafer can be reduced, the qualified rate of the GaN epitaxial wafer is improved, the surface of the epitaxial layer becomes flat,and the appearance is better.

Provided is a memory device including a substrate, a first stack structure, and a plurality of second stack structures. The substrate has a first region and a second region. The first stack structure is located on the substrate of the first region. The second stack structures are located on the substrate of the second region. A sidewall of the first stack structure and a sidewall of the second stack structure have a concave-and-convex surface respectively.

The invention discloses a technological method for planarization of a radio frequency LDMOS polysilicon channel. After polysilicon deposition is carried out, in order to carry out planarization processing on a surface of a polysilicon channel, the method is implemented by the following steps that: (1), a bottom organic antireflective layer is coated; (2), etchback is carried out on the bottom organic antireflective layer; (3), main etching is carried out on the polysilicon to remove polysilicon that is outside the channel; and (4), over etching is carried out on the polysilicon to enable the polysilicon surface inside the channel to be planarized. According to the method provided in the invention, before the etchback of the polysilicon, the bottom organic antireflective layer is coated to carry out planarization; and a dry etching technology with a low selection ratio is utilized to carry out etchback, so that roughness drop of the polysilicon surface inside the channel is reduced; therefore, continuous metal silicide can be formed; and objectives that conductive resistance of the RF LDMOS is reduced and a subsequent technological window is increased can be achieved.

The invention discloses a forming method for a memory cell of a flash memory. The forming method comprises the steps of: providing a semiconductor substrate; forming a first insulating layer on the surface of the semiconductor substrate; forming a floating gate polycrystalline silicon layer on the surface of the first insulating layer; forming a stress layer on the surface of the floating gate polycrystalline silicon layer; after the forming of the stress layer, conducting thermal annealing on the stress layer, the floating gate polycrystalline silicon layer, the first insulating layer and the semiconductor substrate; after thermal annealing, removing the stress layer; after the removal of the stress layer, forming a source line layer passing through the floating gate polycrystalline silicon layer and the first insulating layer on the surface of the semiconductor substrate; and removing part of the floating gate polycrystalline silicon layer and forming a floating gate layer on the surface of the first insulating layer on two sides of the source line layer, wherein the floating gate layer is electrically isolated from the source line layer. The forming method for the memory cell of the flash memory can retain stress inside the floating gate layer, thereby enhancing the channel carrier mobility of the memory cell of the flash memory and reducing the size of the memory cell of the flash memory simultaneously when improving the data retention.