3D NAND memory array common source forming method

Abstract

The invention discloses a 3D NAND memory array common source forming method. The method comprises steps: a substrate is provided, wherein a stacked structure is formed on the substrate, and a gate separation slot exposing the surface of the substrate is formed in the stacked structure; metal contact layers are formed on the surface of the side wall and the bottom of the gate separation slot and the surface of the stacked structure; a polysilicon layer covering the metal contact layer is formed, wherein the polysilicon layer fills the gate separation slot; the polysilicon layer with a partial thickness in the gate separation slot is etched back and removed, and the metal contact layer is used as an etching stop layer; and a metal plug is formed on the etched polysilicon layer. The array common source forming process is simplified.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming an array common source of a 3D NAND memory. Background technique [0002] NAND flash memory is a better storage device than hard disk drives, and it has been widely used in electronic products as people pursue non-volatile storage products with low power consumption, light weight and high performance. At present, the planar NAND flash memory is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND memory is proposed. [0003] At present, the main components of 3D NAND memory can include array storage units and peripheral circuits, and the data access operations in each storage unit are realized through the control of peripheral circuits. Therefore, in the manufacturing process of 3D NAND memory, the conductance of each part Rate is an important link that cannot be...

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Problems solved by technology

[0004] Among them, the Array Common Source (ACS for short) is an important structure requiring high conductivity. Currently, there are many schemes for forming the Array Common Source. In the first scheme, ACS is usually filled with tungsten (W). , although tungsten has good electrical conductivity, in the process of its formation, due to the large stress, it will cause various process problems, such as wafer warping and sliding, photolithography deformation, stacking dislocation, etc., which will lead to device performance degradation of

Therefore, in the second solution, polysilicon is used to replace tungsten, but the conductivity of polysilicon is much lower than that of tungsten. Even if doped polysilicon is used, its conductivity is still much lower than that of tungsten, and the production cost is relatively high.

[0005] The third solution takes both stress and resistance into account. This solution is to form the common source of the array by forming polysilicon and metal plugs on the polysilicon. However, the steps for forming the common source of the array in this solution are more complicated and increase the process cost

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