68results about How to "Reduce the amount of etching" patented technology

The present invention provides one kind of magnetically controlled sputtering process of making printed circuit board. The process includes the following steps: drilling holes on the single layer base material; magnetically controlled sputtering the bottom dielectric and metal layer on the drilled single layer base material; magnetically controlled sputtering conducting copper layer on the single layer base material; drilling holes on multilayer board; magnetically controlled sputtering bottom dielectric and metal layer on the drilled multilayer board; magnetically controlled sputtering conducting copper layer on the drilled multilayer board; and repeating the foregoing steps until reaching the required layer number of the printed circuit board. The present invention combines unique hole forming method and sputtering method and has raised copper-plating and hole-metallizing efficiency, raised reliability and high fine circuit making capacity.

A manufacturing method for a semiconductor device that includes a crystal of metal-insulator phase transition material as a resistor, the method having the steps of forming an electrode on a semiconductor substrate, forming an insulating film on the electrode, forming a through-hole in the insulating film so as to expose the electrode, and housing the crystal in the through-hole so as to contact the electrode.

A display substrate includes a data pad on a base substrate, a first buffer layer which covers the data pad, a second buffer layer pattern which is disposed on the first buffer layer and separated from the data pad in a plan view, an active layer on the second buffer layer pattern, a gate insulation layer pattern on the active layer, both ends of the active layer exposed by the gate insulation layer pattern, and a gate electrode on the gate insulation layer pattern.

A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.

The invention relates to a method for manufacturing flexible printing circuit board by half addition style, and the flexible printing circuit board metal wiring pattern manufactured therefor. The metal wiring pattern of flexible printing circuit board for tape carrier semiconductor package is formed on insulation sheet and takes on multiple stripe appearance. At least one surface of the insulation sheet is plated orderly with a first clad layer- a copper layer, a second clad layer- nickel layer, a third clad layer- gold layer, the second clad layer and the third clad layer wraps upper surface and side surface of the first clad layer. The invention also discloses a method for manufacturing single-sided and double-faced printing circuit board for manufacturing the wiring pattern.

A substrate treatment apparatus for removing an unnecessary substance from a surface of a substrate. The apparatus is provided with: an oxidation liquid supply mechanism for supplying an oxidation liquid having an oxidative effect to the substrate surface; a physical cleaning mechanism for physically cleaning the substrate surface; and an etching liquid supply mechanism for supplying an etching liquid having an etching effect to the substrate surface. It is preferred to physically clean the substrate surface while supplying the oxidation liquid to the substrate surface.

A prepreg containing: a resin composition; and a woven fabric base material. The resin composition contains: (A) at least one of an epoxy resin having a naphthalene skeleton and a phenolic curing agent having a naphthalene skeleton; (B) a high molecular weight compound having at least structures represented by formulae (1) and (2 ) or at least a structure represented by the formula (2), no unsaturated bond between carbon atoms, and a weight-average molecular weight of 250,000 to 850,000; and (C) an inorganic filler. (C) The inorganic filler is subjected to surface treatment with a silane coupling agent represented by a formula (3).

The invention discloses a method for a part to prevent a gap below a side wall barrier layer during a self-aligning silicide process. The part comprises a bedding oxidation film which covers a part underlayer and a grid which is formed on the bedding oxidation film. The method comprises the following steps that: after a sacrificial layer TEOS is deposited, the sacrificial layer and the bedding oxidation film covering the part underlayer are etched until the surface of the part underalyer and the grid top part; and during the manufacturing process of the side wall barrier layer of the grid, by utilizing the self-aligning silicide way, the thickness of the oxidation layer which is deposited on the part underlayer which is etched in a wet way is more than or equal to 100 angstroms and is less than 200 angstroms. The method can prevent the gap below the barrier layer during the self-aligning process of silicide.

The invention discloses a manufacturing method of a trench type double-layer gate MOSFET, which comprises the following steps of: forming a plurality of trenches which comprise a plurality of gate trenches and at least one source lead-out trench; forming a bottom dielectric layer and source polysilicon; forming an inter-polycrystalline silicon oxide layer by adopting an HDP CVD deposition and backetching process; forming a gate dielectric layer; performing polycrystalline silicon deposition to form a second polycrystalline silicon layer; etching back the second polycrystalline silicon layer,forming a polycrystalline silicon gate by the second polycrystalline silicon layer filled in the gate trench after etching back, and reserving the remaining second polycrystalline silicon layer on theside surface of the source lead-out trench; carrying out growth of an under-metal dielectric layer, wherein the growth thickness being greater than a target thickness, and the growth thickness of theunder-metal dielectric layer satisfying complete filling of a gap region in the source lead-out trench; carrying out wet etching to reduce the thickness of the metal lower dielectric layer to a target thickness; performing etching to form an opening of the contact hole, and filling metal. The process cost can be reduced, and the product quality can be improved.

The invention relates to an etching solution for a general resistance silicon product. The etching solution is composed of ammonium bifluoride, potassium nitrate, sulfuric acid, ammonium persulfate, polyethylene glycol, phosphoric acid and a propylene glycol block polyether aqueous solution. According to the characteristics of common resistance silicon products, the traditional etching solution prepared from high-concentration and high-corrosivity hydrofluoric acid, nitric acid, acetic acid and water is improved, a certain amount of HF can be generated according to a certain rate when ammonium bifluoride and sulfuric acid are properly proportioned, and a small amount of potassium nitrate, ammonium persulfate and phosphoric acid are proportioned for etching. The spots or chromatic aberration phenomena generated in incomplete or uneven etching are reduced. The reaction is uniform and mild, the roughness is consistent with that before etching, and the roughness is not increased.

The invention discloses a method for manufacturing a suspension micro electromechanical structure, which comprises the following steps: firstly, at least one insulation layer internally provided with a metal micro electromechanical structure is formed on the upper surface of a silicon fundus, the micro electromechanical structure comprises at least one microstructure and at least one metal sacrifice structure which are independent with each other, and the metal sacrifice structure is internally provided with metal layers and metal bolt layers connecting the metal layers; secondly, at least one blocking layer is made on the upper surface of the insulation layer; thirdly, at least one etching blocking layer is made on the lower surface of the silicon fundus; fourthly, etching is carried out to the lower surface of the silicon fundus to form a space corresponding to the inner suspension microstructure of the micro electromechanical structure; and finally, etching is carried out to the metal sacrifice structure to form the suspension of the micro electromechanical structure. The invention can effectively avoid the improper erosion of the suspension micro electromechanical structure and the surrounding insulation layer thereof, reduce the exposure rate of the suspension micro electromechanical structure, and reduce the final encapsulation cost by being integrated with common integrated circuit packaging.

The invention discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a semiconductor substrate, a gate stack structure, multiple channel columns and a gate isolation structure, wherein the gate stack structure is located on the semiconductor substrate and includes gate conductor layers and interlayer insulation layers which are alternately stacked; the multiple channel columns run through the gate stack structure and is contacted with the semiconductor substrate; the gate isolation structure runs through the gate stack layer to divide a plurality of memory areas and includes a conductive channel and an isolation layer which are formed in a grid line slit, the conductive channel is contacted with the semiconductor substrate, the isolation layer mutually isolates the gate conductor layer from the conductive channel, the grid line slit is disconnected in a predetermined area to form a gap so as to enable the gate conductor layer located in different memory areas to be electrically connected at the gap, the grid line slit includes an end part close to the gap, an extension part and a connecting part used for connecting the end part and the extension part, the channel size of the connecting part close to the end part is less than the channel size thereof close to the extension part so as to limit the cavity volume of the end part, thereby improving the uniformity of the thickness of the isolation layer.

Disclosed is a substrate processing device that can directly detect the concentration of a processing liquid, and thus is able to perform independent concentration control mostly without being affected by the temperature of the processing liquid, and is able to accurately perform chemical processing of a substrate. The substrate processing device, which processes by immersing the substrate in the processing liquid comprising a mixture of a chemical and a diluting liquid, is provided with: a processing tank (1) that retains the processing liquid; heating means (2, 3) that heat the processing liquid; a temperature detection means (4) that detects the temperature of the processing liquid; a temperature control means (5) that operates the aforementioned heating means (2, 3) in a manner so that the detected temperature approaches a set temperature; a replenishing means (6) that replenishes the diluting liquid in the processing liquid; a concentration detection means (7) that detects the concentration of the processing liquid by measuring the light absorption characteristics of the processing liquid; and a concentration control means (8) that operates the aforementioned replenishing means (6) in a manner so that the detected concentration approaches a set concentration.