Manufacturing method of trench type double-layer gate MOSFET

Abstract

The invention discloses a manufacturing method of a trench type double-layer gate MOSFET, which comprises the following steps of: forming a plurality of trenches which comprise a plurality of gate trenches and at least one source lead-out trench; forming a bottom dielectric layer and source polysilicon; forming an inter-polycrystalline silicon oxide layer by adopting an HDP CVD deposition and backetching process; forming a gate dielectric layer; performing polycrystalline silicon deposition to form a second polycrystalline silicon layer; etching back the second polycrystalline silicon layer,forming a polycrystalline silicon gate by the second polycrystalline silicon layer filled in the gate trench after etching back, and reserving the remaining second polycrystalline silicon layer on theside surface of the source lead-out trench; carrying out growth of an under-metal dielectric layer, wherein the growth thickness being greater than a target thickness, and the growth thickness of theunder-metal dielectric layer satisfying complete filling of a gap region in the source lead-out trench; carrying out wet etching to reduce the thickness of the metal lower dielectric layer to a target thickness; performing etching to form an opening of the contact hole, and filling metal. The process cost can be reduced, and the product quality can be improved.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a trench type double-layer gate MOSFET. Background technique [0002] The existing first manufacturing method of trench double-layer gate MOSFET: [0003] Such as Figure 1A to Figure 1F Shown is a schematic diagram of the device structure in each step of the existing first trench type double-layer gate MOSFET manufacturing method; the existing first trench type double-layer gate MOSFET manufacturing method includes the following steps: [0004] Step 1, such as Figure 1A As shown, a plurality of trenches 102 are formed on a semiconductor substrate 101 by photolithography definition plus etching process, and the trenches 102 include a plurality of gate trenches and at least one source extraction trench, and the gate trenches are formed in In the device unit area, the source extraction trench is located outside the device...

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Problems solved by technology

[0044] Although the existing second method does not need to use a single photolithography process to protect the top of the source extraction trench before performing the etching back of the inter-polysilicon oxide layer 205; however, since the width of the source extraction trench 202b is enlarged, After the second polysilicon layer 207 is filled in step five, a gap region will be formed on the top of the source extraction trench 202b, and the gap region will increase after the second polysilicon layer 207 is etched back, which will make the growth in step seven After the metal lower dielectric layer 208, it cannot be guaranteed that the metal lower dielectric layer 208 will completely fill the gap area at the top of the source extraction trench 202b, which will affect the stability of the subsequent first contact hole, thereby affecting the quality of the product

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