Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Hiro

46results about How to "Prevent side erosion" patented technology

High-stability OLED device and preparation method thereof

The invention provides a high-stability OLED device and a preparation method thereof. The high-stability OLED device comprises a substrate and a packaging cover plate 10, wherein the substrate is divided into a pixel region and a packaging region; the substrate and the packaging cover plate are connected through a sealing medium; a first electrode layer, an organic light-emitting layer and a second electrode layer are overlapped on the pixel region on the substrate; and a buffer layer is arranged between the first electrode layer and the substrate. Through the arrangement of the buffer layer,the lateral erosion phenomenon caused by dry etching of the auxiliary electrode layer is solved, and meanwhile, metal ions of the glass substrate are blocked from permeating into the first electrode layer, and electrochemical corrosion is avoided; by adding the auxiliary electrode, the brightness uniformity of a screen body is improved; a pixel defining layer is simultaneously arranged on the first electrode layer and the auxiliary electrode layer and is in direct contact with the buffer layer, so that a very good surrounding structure is formed for an effective pixel region and/or pixels of the OLED, volatile gas outgas is prevented from being released into the pixels to cause pixel shrinkage, and the reliability of the screen body of the OLED is improved.
Owner:GUAN YEOLIGHT TECH CO LTD

Manufacturing method for infrared light emitting diode with embedded extended electrode

InactiveCN104201268ATroubleshoot falling technical issuesPrevent side erosionSemiconductor devicesPower flowOhmic contact
The invention discloses a manufacturing method for an infrared light emitting diode with an embedded extended electrode. The manufacturing method for the infrared light emitting diode with the embedded extended electrode includes that forming a corrosion resisting layer, an armoring layer, an ohmic contact layer, a first current extension layer, a first limit layer, an active layer, a second limit layer and a second current extension layer on an epitaxial substrate in sequence; forming a metal reflector layer on the second current extension layer through evaporation; bonding a metal reflecting layer to a base plate; removing the epitaxial substrate and corrosion resisting layer to expose the armoring layer; forming an extended electrode pattern channel in the surface of the armoring layer, wherein the channel is deep enough to expose the ohmic contact layer; evaporating metal material in the channel to form the extended electrode; manufacturing a bonding pad electrode at the surface of the armoring layer, and communicating the bonding pad electrode with the extended electrode; evaporating a back electrode at the back of the base plate, removing protecting layers of the bonding pad electrode and extended electrode, and shredding to obtain the infrared light emitting diode with the embedded extended electrode. The manufacturing method for the infrared light emitting diode with the embedded extended electrode is capable of improving the reliability of the extended electrode, obtaining better current extension effect and improving the light emitting efficiency of the infrared light emitting diode.
Owner:XIAMEN CHANGELIGHT CO LTD

Method for silk-screening solder resist ink on PCB with small-spacing bonding pads

The invention discloses a method for silk-screening solder resist ink on a PCB with small-spacing bonding pads. The method comprises the steps of: performing silk-screening the solder resist ink on the surface of a PCB twice, performing silk-screening the solder resist ink in a bonding pad area for the first time, and performing silk-screening the solder resist ink in a position outside the bonding pad area on the PCB for the second time, wherein the first silk-screen printing of the solder resist ink comprises the following steps of: S1, silk-screen printing of ink: silk-screen printing of ink is performed on a position between the adjacent bonding pads in the bonding pad area, and the silk-screen printing ink area is expanded to the bonding pads; S2, pre-drying treatment: the silk-screenprinting ink is dried to be a non-sticky object; S3, exposure processing: ink silk-screened in the area between the bonding pads is exposed, and the exposure area is expanded to the bonding pads; S4,developing treatment: the oil ink on the bonding pads and on the outer side of the bonding pads is removed through a developing solution; S5, curing treatment: curing treatment is performed on the ink left by development between the bonding pads and on the bonding pads; and S6, polishing treatment: polishing and removing the ink cured on the bonding pads are performed. The method for silk-screening solder resist ink on the PCB with small-spacing bonding pads is used for PCB silk-screen solder resist ink of small-spacing bonding pads.
Owner:惠州美锐电子科技有限公司

Manufacturing method of printed circuit conductive circuit

The invention discloses a manufacturing method of a printed circuit conductive circuit, and relates to the technical field of printed circuit board manufacturing. The method comprises the following steps: (1) growing a tin seed layer on the surface of a printed circuit insulating substrate; (2) covering the tin seed layer with a patterned dry film; (3) electroplating copper to form a copper conductive circuit; (4) removing the dry film; (5) carrying out heat treatment on the substrate obtained after the treatment in the previous step, so that the copper conductive circuit and the tin seed layer are co-melted into a whole; and 6) etching the tin seed layer to obtain a printed circuit conductive circuit. According to the method, the tin layer etching speed is high, the precision is high, thecircuit is complete and free of side etching, and manufacturing of a high-precision circuit board is facilitated; meanwhile, the copper and the tin are eutectic to form a uniform alloy layer, so thatthe stress between the metals is released, the local defect caused by inconsistent etching speeds of the tin seed layer and the copper conductive wire is prevented, the binding force of the conductive circuit and a bottom layer insulating medium is ensured, and the circuit pattern is good in heat resistance, high in stability and high in reliability.
Owner:UNIV OF ELECTRONIC SCI & TECH OF CHINA

Semiconductor memory

PendingCN110797340ADecrease indentation depthPrevent side erosionTransistorBit lineEtching
The invention provides a semiconductor memory structure, which comprises a substrate, word lines, bit line contacts and bit lines, and is characterized in that a through channel is formed between every two adjacent word lines, each channel comprises a contact window and an inter-window groove, each inter-window groove is provided with a re-recessed surface relative to the contact window, and the re-recessed depth ranges from 5.8nm to 8.5nm, so that the adjacent bit line contacts are not electrically connected with each other; and the sum of the side etching depths of the bit line contact is indirect proportion to the re-recessing depth of the inter-window grooves in the extension direction of the word lines. The invention further provides another semiconductor memory structure, which is characterized in that the contact window in the channel is provided with a re-recessed surface relative to the inter-window groove, and the re-recessed surface is lower than the surface of an isolationstructure in the channel; and each bit line contact has a vertical sectioning profile in the extension direction of the word lines. By controlling the proportion of the etching agent gas or selectingdifferent etching agents, the problem of serious side etching of the bit line contacts due to the formation of the relatively low re-recessed surface of the inter-window grooves is effectively solved.
Owner:CHANGXIN MEMORY TECH INC

Substrate and preparation method thereof and display panel

The invention provides a substrate and a preparation method thereof, and a display panel. The substrate comprises: a substrate; a first conducting layer which is formed on the substrate and patternedto form a first metal wire, wherein the first conducting layer is of a multi-film-layer structure composed of first metal and second metal, and the surface, away from the substrate, of the first conducting layer is a first metal film layer, wherein the first metal is not easy to etch, and the second metal is easy to etch; an insulating layer formed on the first conducting layer; and a second conducting layer which is formed on the insulating layer and is patterned to form a second metal wire and a first metal protection wire, and the first metal protection wire covers the side edge, which is not covered by the insulating layer, of the first metal wire. The first metal protection line is arranged on the side edge, which is not covered by the insulating layer, of the first metal line, so that the side edge, which is not covered by the insulating layer, of the first metal line is protected, the first metal line is prevented from being laterally etched in the etching process of the secondconducting layer, and the product reliability and the manufacturing yield are improved.
Owner:WUHAN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD

Etching solution, touch panel and manufacturing method of touch panel

The invention discloses an etching solution, a touch panel and a manufacturing method of the touch panel, and the manufacturing method of the touch panel comprises the following steps: providing a substrate which is provided with a display region and a peripheral region; a metal layer and a metal nanowire layer are arranged, the first part of the metal nanowire layer is located in the display region, and the second part of the metal nanowire layer and the metal layer are located in the peripheral region; the patterning step comprises the steps that etching liquid capable of etching the metal layer and the metal nanowire layer is used for forming a plurality of peripheral leads on the metal layer and forming a plurality of etching layers on the second part of the metal layer at the same time, and the etching liquid comprises hydrogen peroxide (0.2-40 wt%), acid (0.2-20 wt%), a metal corrosion inhibitor (0.1-10 wt%) and/or a stabilizing agent (0.1-10 wt%). In addition, the invention also provides an etching solution and a touch panel. Patterning of the metal nanowire layer or the metal layer is directly carried out through the etching liquid, so that the purpose of simplifying the manufacturing process is achieved, and the manufacturing cost is further controlled.
Owner:CAMBRIOS FILM SOLUTIONS CORP

Process for manufacturing graph in circuit burying mode

The invention discloses a process for manufacturing a graph in a circuit burying mode. The process comprises the following steps: pasting copper foils to the two sides of a carrier plate through an adhesive; attaching a dry film to the carrier copper foil, and manufacturing a to-be-plated pattern on the dry film; electroplating the carrier core plate to which the dry film is attached; taking downthe dry film on the carrier core plate plated with the copper layer; laminating the plurality of carrier core plates plated with the copper layers; separating the copper layer on the carrier core plate from the carrier plate; pressing the core plate after the carrier plate is taken out again; drilling a hole in the laminated core plate; cleaning and wetting the drilled hole; attaching dry films tothe surfaces of the two sides of the laminated core plate, and forming holes in the drilled positions of the core plate; carrying out metallization treatment on the holes in the dry film openings inthe core plate; and taking down the dry films on the surfaces of the two sides of the core plate. The method has the advantages that the etching side etching problem is avoided, the manufactured circuit better meets the design requirement, and the capacity of a factory for manufacturing a board with a finer circuit is improved under the condition that traditional PCB equipment conditions are not changed.
Owner:GUANGZHOU TERMBRAY ELECTRONICS TECH CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products