8results about How to "Prevent side erosion" patented technology

A manufacturing method of a package substrate includes forming a heterogeneous layer on a substrate body, forming a first circuit layer on the heterogeneous layer, forming a dielectric layer on the heterogeneous layer, embedding the first circuit layer in the dielectric layer, performing a layer-adding circuit, removing the substrate body and the heterogeneous layer to make the depth of the first circuit layer consistent, and forming a second circuit layer on the substrate body. Therefore, a plurality of solder balls can be combined on the first circuit layer.

This invention provides a method for metal interconnection of flexible circuits, comprising the following steps: coating a first dielectric layer; depositing a first metal layer and photolithographically etching a first metal pattern; coating a second dielectric layer and photolithographically etching interlayer vias; depositing a second metal layer and photolithographically etching a second metal pattern, wherein the second metal pattern overlaps with the first metal pattern; coating a third dielectric layer and photolithographically etching contact windows; and fabricating metal contacts. The beneficial effects of this invention are that the overlapping of the upper and lower metal layer patterns improves the reliability of vertical interconnection between metal layers, reduces lateral etching, improves etching accuracy, effectively avoids open circuits in flexible circuits, enhances the interconnection quality of flexible circuits, improves the fracture resistance of fine lines in flexible circuits, facilitates high-density wiring in flexible circuits, constructs thick electrical contact points, reduces contact resistance, improves signal transmission quality, and enhances the mechanical strength and wear resistance of the contacts.

The invention relates to the field of printed circuit board (PCB) manufacturing, provides a method for improving the dry film pressing effect and etching quality of a non-adhesive layered area of a PCB, and is suitable for PCB production links such as pattern electroplating, dry film pressing and etching. The method comprises the following steps: designing a film used for pattern electroplating, and changing a linear design of the edge of a non-adhesive area into an inverted raised grain or zigzag design so as to disperse and release stress generated during dry film pressing and improve the coverage and the fitting tightness of the dry film in a step area; after the outer-layer base material is pressed and before the dry film is pressed, the thickness of the bottom copper is uniformly reduced, the total amount of copper needing to be etched subsequently is reduced, and the lateral erosion risk caused by the fact that the dry film is not pressed compactly is reduced; the total thickness of the bottom copper and the surface copper of the base material is reduced to 15-20 microns, the total copper height after pattern electroplating is reduced, the absolute offset height between the first electricity and the second electricity is reduced, and the dry film is easy to compact and press-fit without bubbles.

The present invention belongs to the field of semiconductor processing technology, and specifically relates to a low-cost large-area graphene patterning method, comprising the following steps: S1, depositing a layer of aluminum metal as a mask on the surface of a substrate to which a graphene film has been transferred; S2, spin coating a layer of photoresist and photolithography to pattern the aluminum metal mask; S3, etching graphene; S4, cleaning the remaining photoresist and corroding the remaining aluminum metal mask. The present invention uses a metal mask to separate graphene from the photoresist, thereby avoiding direct contact between graphene and photoresist to cause photoresist residue. The obtained graphene surface is cleaner and more consistent. In large-area graphene, the clean and consistent surface ensures the consistency of its electrical, mechanical and other properties, so it is suitable for large-area graphene patterning. The present invention uses aluminum metal material as a mask material, and its material cost is low, and the additional material cost in large-area graphene patterning is limited.

The invention relates to the technical field of circuit boards, in particular to a circuit board etching and tin stripping device which comprises a treatment pond, pier heads, a cross beam, vertical beams, sliding rails and a cross frame, the two vertical beams are arranged on the upper surfaces of the two side ends of the treatment pond respectively, the pier heads are installed at the top ends of the vertical beams, the cross beam is located between the two pier heads, and the sliding rails are arranged on the side surfaces of the vertical beams. The transverse frame is installed at the lower end of the beam. The area, not covered with copper foil, of the circuit board is wrapped and protected through the protective clamp, the copper foil area is completely exposed in the reaction liquid, and the transverse frame controls the soaking depth and time of the circuit board in the reaction liquid through sliding control of the sliding rail; the treatment tank is divided into an upper area and a lower area through the separation filter part, precipitated reactants are intercepted in the lower area of the separation filter part, reaction liquid is supplemented again in the upper area for mixing, and the stability of the quality and the concentration of the reaction liquid is ensured.

The invention discloses a Damascus structure and a manufacturing method and application thereof. The manufacturing method comprises the following steps: forming a first layer of photosensitive material covering an inner layer circuit pattern; exposing, developing and post-curing the first layer of photosensitive material; forming a second layer of photosensitive material covering the first layer of photosensitive material; exposing, developing and post-curing the second layer of photosensitive material; forming a conductive material which fills the cavity and covers the top of the first layer of photosensitive material and the inner layer bonding pad; the conductive material is thinned, polished, and etched such that the top of the second layer of photosensitive material is coplanar with the top of the conductive material. The manufactured Damascus structure is not limited by the analysis and attachment capability of the anti-corrosion layer, and an embedded fine circuit layer with a fine line width interval within 8 / 8 microns can be realized; the manufacturing period of the substrate can be shortened, packaging with higher line density is achieved, cost is saved, the line type of a product line layer is better, and loss is lower.

The invention relates to a high-brightness-ratio chip coarsening etching solution and a preparation method and application thereof, and the high-brightness-ratio chip coarsening etching solution comprises the following components by weight: 20-50 parts of quaternary ammonium hydroxide; 20-50 parts of ammonium salt; 1-15 parts of a buffer agent; 0.1 to 1 part of a surfactant; and 30-50 parts of ultrapure water. The addition of the buffer agent can inhibit the generation of precipitates, balance the pH and Factivity, control the etching rate, form a uniform and fine pyramid structure on the surface of the epitaxial layer, and avoid the problem of over-etching caused by too fast local micro-chemical reaction; and meanwhile, the buffer agent can also enable the quaternary ammonium hydroxide to be uniformly adsorbed on the LED chip, so that further lateral erosion is avoided.

The invention discloses a method for processing semiconductor surface defects and a method for preparing semiconductor devices, wherein the method for processing semiconductor surface defects comprises: placing a semiconductor device in a plasma processing device, wherein the semiconductor device comprises a substrate and a deposition layer formed on the surface of the substrate, wherein the deposition layer is provided with bubbles; and plasma bombarding the surface of the deposition layer to break the bubbles, thereby making the surface of the deposition layer flat. The method for processing semiconductor surface defects according to an embodiment of the present invention can make the semiconductor surface flatter and improve the yield of semiconductor devices.