710 results about "Glass etching" patented technology

A micro structure manufacture method includes the steps of: (a) preparing an etching object having an etching target film, provided with a lower hard mask layer and an upper hard mask layer stacked on the etching target film; (b) forming a resist pattern above the etching object; (c) etching the upper hard mask film by using the resist pattern as an etching mask to form an upper hard mask; (d) after the step (c), removing the resist pattern; (e) after the step (d), thinning the upper hard mask by etching; (f) etching the lower hard mask film by using the thinned upper hard mask as an etching mask to form a lower hard mask; and (g) etching the etching target film by using the upper hard mask and the lower hard mask as an etching mask, wherein the upper hard mask film is capable of being more easily etched, using the resist pattern as a mask, than the lower hard mask film. The micro structure manufacture method can etch a fine pattern with good yield.

Embodiments described herein relate to a substrate processing system that integrates substrate edge processing capabilities. Illustrated examples of the processing system include, without limitations, a factory interface, a loadlock chamber, a transfer chamber, and one or more twin process chambers having two or more processing regions that are isolatable from each other and share a common gas supply and a common exhaust pump. The processing regions in each twin process chamber include separate gas distribution assemblies and RF power sources to provide plasma at selective regions on a substrate surface in each processing region. Each twin process chamber is thereby configured to allow multiple, isolated processes to be performed concurrently on at least two substrates in the processing regions.

Methods of forming a glass article are disclosed. In one embodiment, a method of forming a glass article includes translating a pulsed laser beam on a glass substrate sheet to form a laser damage region between a first surface and a second surface of the glass substrate sheet. The method further includes applying an etchant solution to the glass substrate sheet to remove a portion of the glass substrate sheet about the laser damage region. The method may further include strengthening the glass substrate sheet by an ion-exchange strengthening process, and coating the glass substrate sheet with an acid-resistant coating. Also disclosed are methods where the laser damage region has an initial geometry that changes to a desired geometry following the reforming of the glass substrate sheet such that the initial geometry of the laser damage region compensates for the bending of the glass substrate sheet.

Methods for anisotropically etching a tungsten-containing material (such as doped or undoped tungsten metal) include cyclic treatment of tungsten surface with Cl₂ plasma and with oxygen-containing radicals. Treatment with chlorine plasma is performed while the substrate is electrically biased resulting in predominant etching of horizontal surfaces on the substrate. Treatment with oxygen-containing radicals passivates the surface of the substrate to etching, and protects the vertical surfaces of the substrate, such as sidewalls of recessed features, from etching. Treatment with Cl₂ plasma and with oxygen-containing radicals can be repeated in order to remove a desired amount of material. Anisotropic etching can be performed selectively in a presence of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

A process is provided for depositing an undoped silicon oxide film on a substrate disposed in a process chamber. A process gas that includes SiF₄, H₂, a silicon source, and an oxidizing gas reactant is flowed into the process chamber. A plasma having an ion density of at least 10¹¹ ions/cm³ is formed from the process gas. The undoped silicon oxide film is deposited over the substrate with the plasma using a process that has simultaneous deposition and sputtering components. A temperature of the substrate during such depositing is greater than 450° C.

A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surface. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, and TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the sane reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

A method and composition for removing copper-containing post-etch and/or post-ash residue from patterned microelectronic devices is described. The removal composition includes a diluent, a solvent and a copper corrosion inhibitor, wherein the diluent may be a dense fluid or a liquid solvent. The removal compositions effectively remove the copper-containing post-etch residue from the microelectronic device without damaging exposed low-k dielectric and metal interconnect materials.

The formulations of the present invention etch doped silicon oxide compounds, such as BPSG and PSG layers, at rates greater than or equal to the etch rate of undoped silicon oxide such as thermal oxide. The formulations have the general composition of a chelating agent, preferably weakly to moderately acidic (0.1-10%; preferably 0.2-2.8%); a fluoride salt, which may be ammonium fluoride or an organic derivative of either ammonium fluoride or a polyammonium fluoride (1.65-7%; preferably 2.25-7%); a glycol solvent (71-98%; preferably 90-98%); and optionally, an amine.

The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes. The method is also useful whenever it is necessary to maintain tight control over the dimensions of the shaped opening.

A MEMS fabrication process eliminates through-wafer etching, minimizes the thickness of silicon device layers and the required etch times, provides exceptionally precise layer to layer alignment, does not require a wet etch to release the moveable device structure, employs a supporting substrate having no device features on one side, and utilizes low-temperature metal-metal bonding which is relatively insensitive to environmental particulates. This process provided almost 100% yield of scanning micromirror devices exhibiting scanning over a 12° optical range and a mechanical angle of ^±3° at a high resonant frequency of 2.5 kHz with an operating voltage of only 20 VDC.

An integrated copper deposition process, particularly useful for forming a copper seed layer in a narrow via prior to electrochemical plating of copper, including at least one cycle of sputter deposition of copper followed by sputter etching of the deposited copper, preferably performed in a same sputter chamber. The deposition is performed under conditions promoting high copper ionization fractions and strong wafer biasing to draw the copper ions into the via. The etching may be done with argon ions, preferably inductively excited by an RF coil around the chamber, or by copper ions, which may be formed with high target power and intense magnetron or by use of the RF coil. Two or more cycles of deposition/etch may be performed. A final flash deposition may be performed with high copper ionization and low wafer biasing.

A plasma etch process etches high aspect ratio openings in a dielectric film on a workpiece in a reactor having a ceiling electrode overlying the workpiece and an electrostatic chuck supporting the workpiece. The process includes injecting a polymerizing etch process gas through an annular zone of gas injection orifices in the ceiling electrode, and evacuating gas from the reactor through a pumping annulus surrounding an edge of the workpiece. The high aspect ratio openings are etched in the dielectric film with etch species derived from the etch process gas while depositing a polymer derived from the etch process gas onto the workpiece, by generating a plasma in the reactor by applying VHF source power and/or HF and/or LF bias power to the electrodes at the ceiling and/or the electrostatic chuck. The process further includes slowing the deposition rate of the polymer, minimizing etch stop and/or increasing the etch rate in a region of the workpiece typically the center by injecting oxygen or nitrogen and/or high-fluorine containing gas through gas injection orifice in the corresponding region of the ceiling electrode, and adjusting the flow rate of the oxygen or nitrogen and/or high-fluorine containing gas through the gas injection orifice to minimize the difference between profiles and etch depths at the workpiece center and the workpiece periphery.

Methods are provided for fabricating FinFETs that avoid thickness uniformity problems across a die or a substrate. One method includes providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines. The substrate is etched to form a plurality of fins, each of the fins extending uniformly across the width of the chips. An oxide is deposited to fill between the fins and is etched to recess the top of the oxide below the top of the fins. An isolation hard mask is deposited and patterned overlying the plurality of fins and is used as an etch mask to etch trenches in the substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins. The trenches are filled with an insulating material to isolate between adjacent active areas.

The present invention relates to a novel printable paste composition and its use in etching conductive films formed by a plurality of interconnecting silver nano-wires. After etching, the conductive film has a pattern of conductive and non-conductive areas with low visibility. The etched films are suitable as a transparent electrode in visual display devices such as touch screens, liquid crystal displays, plasma display panels and the like.

The present invention provides a method by which a thin film process can be conducted simply and accurately without using resist. Further, the present invention provides a method of manufacturing semiconductor devices at low cost. A first layer is formed over a substrate, a peeling layer is formed over the first layer, the peeling layer is selectively irradiated with a laser beam from the peeling layer side to reduce adhesiveness of a part of the peeling layer. Next, the peeling layer in the part with reduced adhesiveness is removed, and the left portion of the peeling layer is used as a mask to selectively etch the first layer.

A laser direct write method creates true three dimensional structures within photocerams using an focused pulsed ultraviolet laser with a wavelength in a weakly absorbing region of the photoceram material. A critical dose of focused laser UV light selectively exposes embedded volumes of the material for subsequent selective etching. The photoceram material exposure is nonlinear with the laser fluence and the critical dose depends on the square of the per shot fluence and the number of pulses. The laser light is focused to a focal depth for selective volumetric exposure of the material within a focal volume within the remaining collateral volumes that is critically dosed for selecting etching and batch fabrication of highly defined embedded structures.