Semiconductor device, manufacturing method thereof, and data processing system

Abstract

A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.

Description

[0001]This application is based upon and claims the benefit of priority from Japanese patent application No. 2008-103284, filed on Apr. 11, 2008, the disclosure of which is incorporated herein in its entirety by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]This invention relates to a semiconductor device, a manufacturing method thereof, and a data processing system. More particularly, this invention relates to a semiconductor device having wiring lines the surfaces of which are covered with a protecting insulation film, a manufacturing method thereof, and a data processing system including such a semiconductor device.[0004]2. Description of the Related Art[0005]Recent progress in miniaturization of semiconductor devices has made it difficult to form hole patterns solely with photolithography. In cell arrays of a memory product such as a DRAM, in particular, a hole pattern having holes arranged with minimum pitches must be formed in spaces of wiring lines...

AI Technical Summary

Benefits of technology

[0014]In exemplary embodiments, a pattern used to etch the first interlayer insulation film for formation of contact holes and via holes for accommodating conductive plugs is a slit pattern extending in an orthogonal direction to the wiring layer. Therefore, the misalignment in this direction is prevented. Further, since the pattern is a line pattern, a sufficient photolithographic resolution margin can be ensured easily for miniaturization of the semiconductor device, and the opening ability for the etching process also can be ensured easily. Further, during the slit

Problems solved by technology

Recent progress in miniaturization of semiconductor devices has made it difficult to form hole patterns solely with photolithography.

Therefore, the hole size is reduced significantly, which makes it difficult to form the hole pattern only with photolithography.

This makes it difficult to leave the SiN film with a sufficient thickness so as not to expose the wiring layer ultimately.

If the initial thickness of the SiN film is increased to ensure the SiN film is left with a sufficient thickness, it becomes difficult to fill the narrow spaces between the wiring layers arranged with a minimum pitch, with the insulation film.

This poses a problem that the increased t

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