33results about How to "Sufficient process margin" patented technology

A thin film piezoelectric resonator includes a substrate having a cavity; a first electrode extending over the cavity; a piezoelectric film placed on the first electrode; and a second electrode placed on the piezoelectric film, the second electrode having a periphery partially overlapping on the cavity and tapered to have an inner angle of 30 degrees or smaller defined by a part of the periphery thereof and a bottom thereof.

A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.

A semiconductor device having a vertical channel transistor and a method for manufacturing the same are provided. In the semiconductor device, a metal bit line is formed between vertical channel transistors, and the metal bit line is connected to only one of the vertical channel transistors through an asymmetric bit line contact. Through such a structure, the resistance of the bit line can be improved and the process margin for formation of the bit line can be secured.

In a method of manufacturing a semiconductor device including independent gate patterns separated from each other, an active region is defined by forming a field region on a substrate. A gate oxide layer and a polysilicon layer are formed on the substrate. A preliminary gate pattern is formed by partially removing the polysilicon layer along a first direction by a first etching process. A spacer is formed along a side surface of the preliminary gate pattern. A number of separated gate patterns is formed by partially removing the preliminary gate pattern along a second direction crossing the first direction by a second etching process. The gate patterns overlap with the active regions and are separated from each other. Therefore, the overlap margin is increased, and the polysilicon layer is prevented from being over-etched when it is patterned to form the gate pattern.

Disclosed is a display device with high resolution. The display device includes a substrate, a plurality of signal lines on the substrate, multiple buffer layers including at least one organic buffer layer and at least one inorganic buffer layer, and at least one transistor that overlaps one or more of the plurality of signal lines, with the multiple buffer layers interposed therebetween. Accordingly, it may be possible to ensure a sufficient process margin and consequently to realize a high resolution and improve production yield.

A semiconductor memory device includes unit active regions, word lines extending in a first direction over the unit active region, bit lines extending on the word lines in a second direction substantially perpendicularly to the first direction, first pad contacts in contact with central portions of the unit active regions, the first pad contacts being arranged between the word lines, direct contacts electrically connected between the first pad contacts and the bit lines, second pad contacts in contact with edge portions of the unit active regions, the second pad contacts being arranged between the word lines and between the bit lines, buried contacts electrically connected to the second pad contacts, and capacitors electrically connected to the buried contacts.

A display device and a manufacturing method thereof, include a first thin film transistor including a first control electrode, a first semiconductor disposed on the first control electrode, and a first input electrode and a first output electrode opposite to each other on the first semiconductor; and a second thin film transistor including a second control electrode, a second semiconductor disposed on the second control electrode, and a second input electrode and a second output electrode opposite to each other on the second semiconductor, wherein the first semiconductor includes a first lower semiconductor including polysilicon, and a first upper semiconductor disposed on the first lower semiconductor, the first upper semiconductor including amorphous silicon.

A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.