34results about How to "Sufficient process margin" patented technology

A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.

A display device and a manufacturing method thereof, include a first thin film transistor including a first control electrode, a first semiconductor disposed on the first control electrode, and a first input electrode and a first output electrode opposite to each other on the first semiconductor; and a second thin film transistor including a second control electrode, a second semiconductor disposed on the second control electrode, and a second input electrode and a second output electrode opposite to each other on the second semiconductor, wherein the first semiconductor includes a first lower semiconductor including polysilicon, and a first upper semiconductor disposed on the first lower semiconductor, the first upper semiconductor including amorphous silicon.

A thin film piezoelectric resonator includes a substrate having a cavity; a first electrode extending over the cavity; a piezoelectric film placed on the first electrode; and a second electrode placed on the piezoelectric film, the second electrode having a periphery partially overlapping on the cavity and tapered to have an inner angle of 30 degrees or smaller defined by a part of the periphery thereof and a bottom thereof.

It is a main object of the present invention to provide a polyimide precursor and a polyimide precursor resin composition, which precursor being easy to synthesize, available at low cost, excellent in storage and capable of giving polyimide that is low in impurities after imidization, irrespective of the chemical structure of the finally-obtained polyimide.It is another object of the present invention to provide a polyimide precursor having repeating units represented by the following formula (1) and a photosensitive resin composition comprising the polyimide precursor and a photoacid generator or photobase generator:In the formula (1), R1 is a tetravalent organic group; R2 is a divalent organic group; R1s may be the same or different from each other and R2 s may be the same or different from each other in the repeating units; R3 and R4 respectively represent a monovalent organic group having a structure represented by the following formula (2) and may be the same or different from each other; and R3s and R4s in the repeating units may be the same or different from each other, respectively. In the formula (2), R5, R6 and R7 respectively represent a hydrogen atom, a halogen atom or a monovalent organic group; R8 is a monovalent organic group; R8s in the repeating units may be the same or different from each other; 35 mole % or less of R8s are organic groups having a reactive group; and R5, R6, R7 and R8 may be bonded to each other to form a ring structure.

A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.

A semiconductor device having a vertical channel transistor and a method for manufacturing the same are provided. In the semiconductor device, a metal bit line is formed between vertical channel transistors, and the metal bit line is connected to only one of the vertical channel transistors through an asymmetric bit line contact. Through such a structure, the resistance of the bit line can be improved and the process margin for formation of the bit line can be secured.

A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.

Provided is a blankmask with a light-shielding layer including a light block layer and an anti-reflective layer, and a hard mask film. The light block layer and the anti-reflective layer are formed by combining a layer formed of a MoSi compound and a layer formed of a MoTaSi compound. Thus, the blankmask enables formation of a pattern of 32 nm or less, since the light-shielding layer can be thinly formed to a thickness of 200 to 700 and a photomask having pattern fidelity corresponding to the resolution of the pattern can be formed. The light-shielding layer has an optical density of 2.0 to 4.0 at an exposure wavelength of 193 nm, chemical resistance, and a sufficient process margin for defect repair. Further, the hard mask film is formed to a thickness of 20 to 50 using a compound including tin (Sn) and chromium (Cr), thereby decreasing an etch rate of the hard mask film. Accordingly, a resist film can be formed as a thin film, thereby manufacturing a high-resolution blankmask.

A semiconductor device includes an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening, a bit line conductive layer that at least partially fills the narrow opening, and a bit line capping layer that fills the groove so that its top surface is as high as that of the insulating layer. Spacers are formed on the inner walls of the wide opening.

A non-volatile semiconductor memory device includes a plurality of lower electrodes arranged in a matrix manner, a plurality of recording layer patterns, each being arranged on the lower electrode, that contain a phase change material, and an interlayer insulation film that is provided between the lower electrode and the recording layer pattern and that has a plurality of apertures for exposing one portion of the lower electrode. The lower electrode and the recording layer pattern are connected in each aperture. The apertures extend in the X direction in parallel to one another. The recording layer patterns extend in the Y direction in parallel to one another. Thus the aperture can be formed with higher accuracy as compared to forming an independent aperture. Accordingly, high heating efficiency can be obtained while effectively preventing occurrence of poor connection or the like.

Disclosed is an organic light-emitting display device capable of realizing a high resolution. The organic light-emitting display device includes a storage capacitor disposed on a substrate, which overlaps at least one transistor, with at least one buffer layer interposed therebetween, the at least one buffer layer disposed on the storage capacitor, and which includes a lower storage electrode and an upper storage electrode overlapping the lower storage electrode, with a storage buffer layer interposed therebetween, and a light-emitting diode connected to the transistor. One of the lower storage electrode and the upper storage electrode is formed to have the same line width and the same shape as the storage buffer layer, thereby ensuring a sufficient process margin and consequently realizing a high resolution and improving production yield.

Disclosed is a display device with high resolution. The display device includes a substrate, a plurality of signal lines on the substrate, multiple buffer layers including at least one organic buffer layer and at least one inorganic buffer layer, and at least one transistor that overlaps one or more of the plurality of signal lines, with the multiple buffer layers interposed therebetween. Accordingly, it may be possible to ensure a sufficient process margin and consequently to realize a high resolution and improve production yield.